Built-in Flows and their Configuration Variables¶

These flows come included with LibreLane. They use a variety of built-in steps to either provide a general RTL-to-GDSII flow or more specific niches.

Each Flow’s list of configuration variables is essentially a sum of:

AND

Flow-specific Configuration Variables
All included Step Configuration Variables

If you’re looking for documentation for the Flow Python classes themselves, check the API reference here.

Flows¶

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Classic¶

A flow of type librelane.flows.SequentialFlow that is the most similar to the original OpenLane flow, running the Verilog RTL through Yosys, OpenROAD, KLayout and Magic to produce a valid GDSII for simpler designs.

This is the default when using LibreLane via the command-line.

Using from the CLI¶

librelane --flow Classic [...]

Importing¶

from librelane.flows import Flow

Classic = Flow.factory.get("Classic")

Flow-specific Configuration Variables¶

Variable Name	Type	Description	Default
`RUN_TAP_ENDCAP_INSERTION` Deprecated names `TAP_DECAP_INSERTION` `RUN_TAP_DECAP_INSERTION`	bool	Enables the OpenROAD.TapEndcapInsertion step.	`True`
`RUN_POST_GPL_DESIGN_REPAIR` Deprecated names `PL_RESIZER_DESIGN_OPTIMIZATIONS` `RUN_REPAIR_DESIGN`	bool	Enables resizer design repair after global placement using the OpenROAD.RepairDesignPostGPL step.	`True`
`RUN_POST_GRT_DESIGN_REPAIR`	bool	Enables resizer design repair after global placement using the OpenROAD.RepairDesignPostGPL step. This is experimental and may result in hangs and/or extended run times.	`False`
`RUN_CTS` Deprecated names `CLOCK_TREE_SYNTH`	bool	Enables clock tree synthesis using the OpenROAD.CTS step.	`True`
`RUN_POST_CTS_RESIZER_TIMING` Deprecated names `PL_RESIZER_TIMING_OPTIMIZATIONS`	bool	Enables resizer timing optimizations after clock tree synthesis using the OpenROAD.ResizerTimingPostCTS step.	`True`
`RUN_POST_GRT_RESIZER_TIMING` Deprecated names `GLB_RESIZER_TIMING_OPTIMIZATIONS`	bool	Enables resizer timing optimizations after global routing using the OpenROAD.ResizerTimingPostGRT step. This is experimental and may result in hangs and/or extended run times.	`False`
`RUN_HEURISTIC_DIODE_INSERTION`	bool	Enables the Odb.HeuristicDiodeInsertion step.	`False`
`RUN_ANTENNA_REPAIR` Deprecated names `GRT_REPAIR_ANTENNAS`	bool	Enables the OpenROAD.RepairAntennas step.	`True`
`RUN_DRT`	bool	Enables the OpenROAD.DetailedRouting step.	`True`
`RUN_FILL_INSERTION`	bool	Enables the OpenROAD.FillInsertion step.	`True`
`RUN_MCSTA` Deprecated names `RUN_SPEF_STA`	bool	Enables multi-corner static timing analysis using the OpenROAD.STAPostPNR step.	`True`
`RUN_SPEF_EXTRACTION`	bool	Enables parasitics extraction using the OpenROAD.RCX step.	`True`
`RUN_IRDROP_REPORT`	bool	Enables generation of an IR Drop report using the OpenROAD.IRDropReport step.	`True`
`RUN_LVS`	bool	Enables the Netgen.LVS step.	`True`
`RUN_MAGIC_STREAMOUT` Deprecated names `RUN_MAGIC`	bool	Enables the Magic.StreamOut step to generate GDSII.	`True`
`RUN_KLAYOUT_STREAMOUT` Deprecated names `RUN_KLAYOUT`	bool	Enables the KLayout.StreamOut step to generate GDSII.	`True`
`RUN_MAGIC_WRITE_LEF` Deprecated names `MAGIC_GENERATE_LEF`	bool	Enables the Magic.WriteLEF step.	`True`
`RUN_KLAYOUT_XOR`	bool	Enables running the KLayout.XOR step on the two GDSII files generated by Magic and Klayout. Stream-outs for both KLayout and Magic should have already run, and the PDK must support both signoff tools.	`True`
`RUN_MAGIC_DRC`	bool	Enables the Magic.DRC step.	`True`
`RUN_KLAYOUT_DRC`	bool	Enables the KLayout.DRC step.	`True`
`RUN_EQY`	bool	Enables the Yosys.EQY step. Not valid for VHDLClassic.	`False`
`RUN_LINTER` Deprecated names `RUN_VERILATOR`	bool	Enables the Verilator.Lint step and associated checker steps. Not valid for VHDLClassic.	`True`

Included Steps¶

VHDLClassic¶

A variant of Classic that accepts VHDL files for Synthesis instead of Verilog files (and removes Verilog linting/equivalence steps.)

Using from the CLI¶

librelane --flow VHDLClassic [...]

Importing¶

from librelane.flows import Flow

VHDLClassic = Flow.factory.get("VHDLClassic")

Flow-specific Configuration Variables¶

Variable Name	Type	Description	Default
`RUN_TAP_ENDCAP_INSERTION` Deprecated names `TAP_DECAP_INSERTION` `RUN_TAP_DECAP_INSERTION`	bool	Enables the OpenROAD.TapEndcapInsertion step.	`True`
`RUN_POST_GPL_DESIGN_REPAIR` Deprecated names `PL_RESIZER_DESIGN_OPTIMIZATIONS` `RUN_REPAIR_DESIGN`	bool	Enables resizer design repair after global placement using the OpenROAD.RepairDesignPostGPL step.	`True`
`RUN_POST_GRT_DESIGN_REPAIR`	bool	Enables resizer design repair after global placement using the OpenROAD.RepairDesignPostGPL step. This is experimental and may result in hangs and/or extended run times.	`False`
`RUN_CTS` Deprecated names `CLOCK_TREE_SYNTH`	bool	Enables clock tree synthesis using the OpenROAD.CTS step.	`True`
`RUN_POST_CTS_RESIZER_TIMING` Deprecated names `PL_RESIZER_TIMING_OPTIMIZATIONS`	bool	Enables resizer timing optimizations after clock tree synthesis using the OpenROAD.ResizerTimingPostCTS step.	`True`
`RUN_POST_GRT_RESIZER_TIMING` Deprecated names `GLB_RESIZER_TIMING_OPTIMIZATIONS`	bool	Enables resizer timing optimizations after global routing using the OpenROAD.ResizerTimingPostGRT step. This is experimental and may result in hangs and/or extended run times.	`False`
`RUN_HEURISTIC_DIODE_INSERTION`	bool	Enables the Odb.HeuristicDiodeInsertion step.	`False`
`RUN_ANTENNA_REPAIR` Deprecated names `GRT_REPAIR_ANTENNAS`	bool	Enables the OpenROAD.RepairAntennas step.	`True`
`RUN_DRT`	bool	Enables the OpenROAD.DetailedRouting step.	`True`
`RUN_FILL_INSERTION`	bool	Enables the OpenROAD.FillInsertion step.	`True`
`RUN_MCSTA` Deprecated names `RUN_SPEF_STA`	bool	Enables multi-corner static timing analysis using the OpenROAD.STAPostPNR step.	`True`
`RUN_SPEF_EXTRACTION`	bool	Enables parasitics extraction using the OpenROAD.RCX step.	`True`
`RUN_IRDROP_REPORT`	bool	Enables generation of an IR Drop report using the OpenROAD.IRDropReport step.	`True`
`RUN_LVS`	bool	Enables the Netgen.LVS step.	`True`
`RUN_MAGIC_STREAMOUT` Deprecated names `RUN_MAGIC`	bool	Enables the Magic.StreamOut step to generate GDSII.	`True`
`RUN_KLAYOUT_STREAMOUT` Deprecated names `RUN_KLAYOUT`	bool	Enables the KLayout.StreamOut step to generate GDSII.	`True`
`RUN_MAGIC_WRITE_LEF` Deprecated names `MAGIC_GENERATE_LEF`	bool	Enables the Magic.WriteLEF step.	`True`
`RUN_KLAYOUT_XOR`	bool	Enables running the KLayout.XOR step on the two GDSII files generated by Magic and Klayout. Stream-outs for both KLayout and Magic should have already run, and the PDK must support both signoff tools.	`True`
`RUN_MAGIC_DRC`	bool	Enables the Magic.DRC step.	`True`
`RUN_KLAYOUT_DRC`	bool	Enables the KLayout.DRC step.	`True`
`RUN_EQY`	bool	Enables the Yosys.EQY step. Not valid for VHDLClassic.	`False`
`RUN_LINTER` Deprecated names `RUN_VERILATOR`	bool	Enables the Verilator.Lint step and associated checker steps. Not valid for VHDLClassic.	`True`

Included Steps¶

Chip¶

A flow of type librelane.flows.SequentialFlow that is used to implement complete chip designs. This includes pad ring generation, seal ring generation, filler insertion, and density check.

Using from the CLI¶

librelane --flow Chip [...]

Importing¶

from librelane.flows import Flow

Chip = Flow.factory.get("Chip")

Flow-specific Configuration Variables¶

Variable Name	Type	Description	Default
`RUN_TAP_ENDCAP_INSERTION` Deprecated names `TAP_DECAP_INSERTION` `RUN_TAP_DECAP_INSERTION`	bool	Enables the OpenROAD.TapEndcapInsertion step.	`True`
`RUN_POST_GPL_DESIGN_REPAIR` Deprecated names `PL_RESIZER_DESIGN_OPTIMIZATIONS` `RUN_REPAIR_DESIGN`	bool	Enables resizer design repair after global placement using the OpenROAD.RepairDesignPostGPL step.	`True`
`RUN_POST_GRT_DESIGN_REPAIR`	bool	Enables resizer design repair after global placement using the OpenROAD.RepairDesignPostGPL step. This is experimental and may result in hangs and/or extended run times.	`False`
`RUN_CTS` Deprecated names `CLOCK_TREE_SYNTH`	bool	Enables clock tree synthesis using the OpenROAD.CTS step.	`True`
`RUN_POST_CTS_RESIZER_TIMING` Deprecated names `PL_RESIZER_TIMING_OPTIMIZATIONS`	bool	Enables resizer timing optimizations after clock tree synthesis using the OpenROAD.ResizerTimingPostCTS step.	`True`
`RUN_POST_GRT_RESIZER_TIMING` Deprecated names `GLB_RESIZER_TIMING_OPTIMIZATIONS`	bool	Enables resizer timing optimizations after global routing using the OpenROAD.ResizerTimingPostGRT step. This is experimental and may result in hangs and/or extended run times.	`False`
`RUN_HEURISTIC_DIODE_INSERTION`	bool	Enables the Odb.HeuristicDiodeInsertion step.	`False`
`RUN_ANTENNA_REPAIR` Deprecated names `GRT_REPAIR_ANTENNAS`	bool	Enables the OpenROAD.RepairAntennas step.	`True`
`RUN_DRT`	bool	Enables the OpenROAD.DetailedRouting step.	`True`
`RUN_FILL_INSERTION`	bool	Enables the OpenROAD.FillInsertion step.	`True`
`RUN_MCSTA` Deprecated names `RUN_SPEF_STA`	bool	Enables multi-corner static timing analysis using the OpenROAD.STAPostPNR step.	`True`
`RUN_SPEF_EXTRACTION`	bool	Enables parasitics extraction using the OpenROAD.RCX step.	`True`
`RUN_IRDROP_REPORT`	bool	Enables generation of an IR Drop report using the OpenROAD.IRDropReport step.	`True`
`RUN_LVS`	bool	Enables the Netgen.LVS step.	`True`
`RUN_MAGIC_STREAMOUT` Deprecated names `RUN_MAGIC`	bool	Enables the Magic.StreamOut step to generate GDSII.	`True`
`RUN_KLAYOUT_STREAMOUT` Deprecated names `RUN_KLAYOUT`	bool	Enables the KLayout.StreamOut step to generate GDSII.	`True`
`RUN_MAGIC_WRITE_LEF` Deprecated names `MAGIC_GENERATE_LEF`	bool	Enables the Magic.WriteLEF step.	`True`
`RUN_KLAYOUT_XOR`	bool	Enables running the KLayout.XOR step on the two GDSII files generated by Magic and Klayout. Stream-outs for both KLayout and Magic should have already run, and the PDK must support both signoff tools.	`True`
`RUN_MAGIC_DRC`	bool	Enables the Magic.DRC step.	`True`
`RUN_KLAYOUT_DRC`	bool	Enables the KLayout.DRC step.	`True`
`RUN_EQY`	bool	Enables the Yosys.EQY step. Not valid for VHDLClassic.	`False`
`RUN_LINTER` Deprecated names `RUN_VERILATOR`	bool	Enables the Verilator.Lint step and associated checker steps. Not valid for VHDLClassic.	`True`

Included Steps¶

OpenInKLayout¶

This ‘flow’ actually just has one step that opens the LEF/DEF from the initial state object in KLayout. Fancy that.

Intended for use with run tags that have already been run with another flow, i.e.:

librelane [...]
librelane --last-run --flow OpenInKLayout [...]

Using from the CLI¶

librelane --flow OpenInKLayout [...]

Importing¶

from librelane.flows import Flow

OpenInKLayout = Flow.factory.get("OpenInKLayout")

Included Steps¶

KLayout.OpenGUI

OpenInOpenROAD¶

This ‘flow’ actually just has one step that opens the ODB from the initial state object in OpenROAD.

Intended for use with run tags that have already been run with another flow, i.e.

librelane [...]
librelane --last-run --flow OpenInOpenROAD [...]

Using from the CLI¶

librelane --flow OpenInOpenROAD [...]

Importing¶

from librelane.flows import Flow

OpenInOpenROAD = Flow.factory.get("OpenInOpenROAD")

Included Steps¶

OpenROAD.OpenGUI

OpenInMagic¶

This ‘flow’ actually just has one step that opens the GDS or DEF from the initial state object in Magic.

Intended for use with run tags that have already been run with another flow, i.e.

librelane [...]
librelane --last-run --flow OpenInMagic [...]

Using from the CLI¶

librelane --flow OpenInMagic [...]

Importing¶

from librelane.flows import Flow

OpenInMagic = Flow.factory.get("OpenInMagic")

Included Steps¶

Magic.OpenGUI

SynthesisExploration¶

Synthesis Exploration is a feature that tries multiple synthesis strategies (in the form of different scripts for the ABC utility) to try and find which strategy is better by either minimizing area or maximizing slack (and thus frequency.)

The output is represented in a tabulated format, e.g.:

┏━━━━━━━━━━━━━━━━┳━━━━━━━┳━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━━━━━━━━━━━━━━┓
┃ SYNTH_STRATEGY ┃ Gates ┃ Area (µm²)    ┃ Worst R2R Setup Slack (ns) ┃ Worst Setup Slack (ns) ┃ Total -ve Setup Slack (ns) ┃
┡━━━━━━━━━━━━━━━━╇━━━━━━━╇━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━━━━━━━━━━━━━━┩
│ AREA 0         │ 6692  │ 88675.046400  │ 8.601737                   │ 8.066582297115897      │ 0.0                        │
│ AREA 1         │ 6776  │ 88750.118400  │ 8.196377                   │ 7.965740292847976      │ 0.0                        │
│ AREA 2         │ 6720  │ 88352.236800  │ 8.628829                   │ 8.628828562575336      │ 0.0                        │
│ AREA 3         │ 11620 │ 110656.128000 │ 8.688749                   │ 8.688749521355085      │ 0.0                        │
│ DELAY 0        │ 6797  │ 91976.963200  │ 8.135016                   │ 8.13501644628924       │ 0.0                        │
│ DELAY 1        │ 6877  │ 92278.502400  │ 8.828732                   │ 8.828731773329311      │ 0.0                        │
│ DELAY 2        │ 6891  │ 92394.864000  │ 8.775793                   │ 6.444352789363264      │ 0.0                        │
│ DELAY 3        │ 6792  │ 91675.424000  │ 9.102930                   │ 8.078121511470991      │ 0.0                        │
│ DELAY 4        │ 8533  │ 98833.539200  │ 8.665778                   │ 8.665778562236717      │ 0.0                        │
└────────────────┴───────┴───────────────┴────────────────────────────┴────────────────────────┴────────────────────────────┘

You can then update your config file with the best SYNTH_STRATEGY for your use-case so it can be used with other flows.

Using from the CLI¶

librelane --flow SynthesisExploration [...]

Importing¶

from librelane.flows import Flow

SynthesisExploration = Flow.factory.get("SynthesisExploration")