Universal Flow PDK Configuration Variables

These are variables that are to be defined by a process design kit’s configuration files for all steps and flows. For a PDK to be compatible with LibreLane, all non-Optional variables must be given a value.

Like with flow configuration variables, configuration objects can freely override these values.

Note

? indicates an optional variable, i.e., a value that does not need to be implemented by a PDK or an SCL. LibreLane steps are expected to understand that these values may hold a value of None in the input configuration and behave accordingly.

PDK-Level

These are variables that affect the entire PDK.

Variable Name	Type	Description	Default	Units
STD_CELL_LIBRARY PDK	str	Specifies the default standard cell library to be used under the specified PDK. Must be a valid C identifier, i.e., matches the regular expression [_a-zA-Z][_a-zA-Z0-9]+.	None
VDD_PIN PDK	str	The power pin for the cells.	None
GND_PIN PDK	str	The ground pin for the cells.	None
TECH_LEFS PDK	Dict[str, Path]	Map of corner patterns to technology LEF files. A corner not matched here will not be supported by OpenRCX in the default flow.	None
PRIMARY_GDSII_STREAMOUT_TOOL PDK Deprecated names PRIMARY_SIGNOFF_TOOL	str	Specify the primary GDSII streamout tool for this PDK. For most open-source PDKs, that would be ‘magic’.	None
DEFAULT_MAX_TRAN PDK	Decimal?	Defines the default maximum transition value used in Synthesis and CTS. A minimum of 0.1 * CLOCK_PERIOD and this variable, if defined, is used.	None	ns
DEFAULT_CORNER PDK	str	The interconnect/process/voltage/temperature corner (IPVT) to use the characterized lib files compatible with by default.	None
STA_CORNERS PDK	List[str]	A list of fully qualified IPVT (Interconnect, transistor Process, Voltage, and Temperature) timing corners on which to conduct multi-corner static timing analysis.	None
RT_MIN_LAYER PDK	str	The lowest metal layer to route on.	None
RT_MAX_LAYER PDK	str	The highest metal layer to route on.	None

SCL-Level

These are variables that affect a specific standard-cell library.

Variable Name	Type	Description	Default	Units
SCL_GROUND_PINS PDK Deprecated names STD_CELL_GROUND_PINS	List[str]	SCL-specific ground pins	None
SCL_POWER_PINS PDK Deprecated names STD_CELL_POWER_PINS	List[str]	SCL-specific power pins	None
TRISTATE_CELLS PDK Deprecated names TRISTATE_CELL_PREFIX	List[str]?	A list of cell names or wildcards of tri-state buffers.	None
FILL_CELLS PDK Deprecated names FILL_CELL	List[str]	A list of cell names or wildcards of fill cells to be used in fill insertion.	None
DECAP_CELLS PDK Deprecated names DECAP_CELL	List[str]	A list of cell names or wildcards of decap cells to be used in fill insertion.	None
LIB PDK	Dict[str, List[Path]]	A map from corner patterns to a list of associated liberty files. Exactly one entry must match the DEFAULT_CORNER.	None
CELL_LEFS PDK Deprecated names CELLS_LEF	List[Path]	Path(s) to the cells’ LEF file(s).	None
CELL_GDS PDK Deprecated names GDS_FILES CELLS_GDS	List[Path]	Path(s) to the cells’ GDSII file(s).	None
CELL_VERILOG_MODELS PDK	List[Path]?	Path(s) to cells’ Verilog model(s)	None
CELL_BB_VERILOG_MODELS PDK	List[Path]?	Path(s) to cells’ black-box Verilog model(s)	None
CELL_SPICE_MODELS PDK	List[Path]?	Path(s) to cells’ SPICE model(s)	None
CELL_CDLS PDK Deprecated names STD_CELL_LIBRARY_CDL	List[Path]?	A circuit-design language view of the standard cell library.	None
SYNTH_EXCLUDED_CELL_FILE PDK Deprecated names NO_SYNTH_CELL_LIST SYNTH_EXCLUSION_CELL_LIST	Path	Path to a text file containing a list of (wildcards matching) cells to be excluded from the lib file in synthesis alone.	None
PNR_EXCLUDED_CELL_FILE PDK Deprecated names DRC_EXCLUDE_CELL_LIST PNR_EXCLUSION_CELL_LIST	Path	Path to a text file containing a list of undesirable or bad (DRC-failed or complex pinout) cells or wildcards matching cells to be excluded from synthesis AND PnR.	None
OUTPUT_CAP_LOAD PDK Deprecated names SYNTH_CAP_LOAD	Decimal	Defines the capacitive load on the output ports.	None	fF
MAX_FANOUT_CONSTRAINT PDK Deprecated names SYNTH_MAX_FANOUT	int	The max load that the output ports can drive to be used as a constraint on Synthesis and CTS.	None	cells
MAX_TRANSITION_CONSTRAINT PDK Deprecated names SYNTH_MAX_TRAN	Decimal?	The max transition time (slew) from high to low or low to high on cell inputs in ns to be used as a constraint on Synthesis and CTS. If not provided, it is calculated at runtime as 10% of the provided clock period, unless that exceeds the PDK’s DEFAULT_MAX_TRAN value.	None	ns
MAX_CAPACITANCE_CONSTRAINT PDK	Decimal?	The maximum capacitance constraint. If not provided, the constraint is not set in the SDC file which will fall back to the value set by the liberty file	None	pF
CLOCK_UNCERTAINTY_CONSTRAINT PDK Deprecated names SYNTH_CLOCK_UNCERTAINTY	Decimal	Specifies a value for the clock uncertainty/jitter for timing analysis.	None	ns
CLOCK_TRANSITION_CONSTRAINT PDK Deprecated names SYNTH_CLOCK_TRANSITION	Decimal	Specifies a value for the clock transition/slew for timing analysis.	None	ns
TIME_DERATING_CONSTRAINT PDK Deprecated names SYNTH_TIMING_DERATE	Decimal	Specifies a derating factor to multiply the path delays with. It specifies the upper and lower ranges of timing.	None
IO_DELAY_CONSTRAINT PDK Deprecated names IO_PCT	Decimal	Specifies the percentage of the clock period used in the input/output delays.	None
SYNTH_DRIVING_CELL PDK	str	The cell to drive the input ports, used in synthesis and static timing analysis, in the format {cell}/{port}.	None
SYNTH_CLK_DRIVING_CELL PDK	str?	The cell to drive the clock input ports, used in synthesis and static timing analysis, in the format {cell}/{port}. If not specified, SYNTH_DRIVING_CELL will be used.	None
SYNTH_TIEHI_CELL PDK	str	Defines the tie high cell followed by the port that implements the tie high functionality, in the format {cell}/{port}.	None
SYNTH_TIELO_CELL PDK	str	Defines the tie high cell followed by the port that implements the tie low functionality, in the format {cell}/{port}.	None
SYNTH_BUFFER_CELL PDK	str	Defines a buffer port to be used by yosys during synthesis: in the format {cell}/{input_port}/{output_port}	None
PLACE_SITE PDK	str	Defines the primary placement site in placement as specified in the technology LEF files, to generate the placement grid.	None
CELL_PAD_EXCLUDE PDK	List[str]	Defines a list of cells to be excluded from cell padding.	None
DIODE_CELL PDK	str?	Defines a diode cell used to fix antenna violations, in the format {cell}/{port}. If not defined, steps should not attempt to repair the antenna effect by inserting diode cells.	None
WELLTAP_CELL PDK Deprecated names FP_WELLTAP_CELL	str?	Defines the cell used for tap insertion. If not defined, steps should not attempt to insert welltap cells.	None
ENDCAP_CELL PDK Deprecated names FP_ENDCAP_CELL	str?	Defines the so-called ‘end-cap’ cell- class of decap cells placed at either sides of a design, if available.	None