Built-in Steps and their Configuration Variables¶

These steps are included with LibreLane and are used by its various built-in flows.

This page documents these steps, how to get them and their configuration variables (if applicable).

If you’re looking for documentation for the Step Python classes themselves, check the API reference here.

Warnings

Two steps in a given Flow may share a configuration variable name if-and-only-if the variables are otherwise identical, i.e., the name, type, and default value all match. Otherwise, the flow will not compile.
Some steps have a variable prefixed with RUN_ that enables or disables said step. This is a vestige from OpenLane and it is recommended to explicitly specify your flow either by using the API or in your JSON configuration file’s meta object.

Notes

? indicates an optional variable, i.e., a value that may hold a value of None. LibreLane steps are expected to understand that these values are optional and behave accordingly.
Variable names denoted (^PDK) are expected to be declared by the PDK.

If a PDK does not define one of the required variables, it is considered to be incompatible with this step.

Tip

For a table of contents, press the following button on the top-right corner of the page:

Checker¶

Disconnected Pins Checker¶

Raises an immediate error if critical disconnected pins (metric: design__critical_disconnected_pin__count) are >= 0. Doesn’t raise an error depending on error_on_var if defined.

Configuration Variables¶

Variable Name	Type	Description	Default
`ERROR_ON_DISCONNECTED_PINS` Deprecated names `QUIT_ON_DISCONNECTED_PINS`	bool	Checks for disconnected instance pins after detailed routing and quits immediately if so.	`True`

Hold Timing Violations Checker¶

Raises a deferred error if NotImplemented (metric: timing__hold_vio__count) are >= 0. Doesn’t raise an error depending on error_on_var if defined.

Configuration Variables¶

Variable Name	Type	Description	Default
`TIMING_VIOLATION_CORNERS` ^PDK Deprecated names `TIMING_VIOLATIONS_CORNERS`	List[str]	A list of wildcards matching IPVT corners to use during checking for timing violations.	`None`
`HOLD_VIOLATION_CORNERS` ^PDK	List[str]?	A list of wildcards matching IPVT corners to use during checking for hold violations.	`['*']`

Spice Extraction-based Illegal Overlap Checker¶

Raises a deferred error if Magic Illegal Overlap errors (metric: magic__illegal_overlap__count) are >= 0. Doesn’t raise an error depending on error_on_var if defined.

Configuration Variables¶

Variable Name	Type	Description	Default
`ERROR_ON_ILLEGAL_OVERLAPS` Deprecated names `QUIT_ON_ILLEGAL_OVERLAPS`	bool	Checks for illegal overlaps during Magic extraction. In some cases, these imply existing undetected shorts in the design. It raises an error at the end of the flow if so.	`True`

KLayout Antenna Checker¶

Raises a deferred error if KLayout antenna errors (metric: klayout__antenna_error__count) are >= 0. Doesn’t raise an error depending on error_on_var if defined.

Configuration Variables¶

Variable Name	Type	Description	Default
`ERROR_ON_KLAYOUT_ANTENNA`	bool	Checks for antenna violations after KLayout antenna check is executed and exits the flow if any was found.	`True`

KLayout Design Rule Checker¶

Raises a deferred error if KLayout DRC errors (metric: klayout__drc_error__count) are >= 0. Doesn’t raise an error depending on error_on_var if defined.

Configuration Variables¶

Variable Name	Type	Description	Default
`ERROR_ON_KLAYOUT_DRC` Deprecated names `QUIT_ON_KLAYOUT_DRC`	bool	Checks for DRC violations after KLayout DRC is executed and exits the flow if any was found.	`True`

KLayout Density Checker¶

Raises a deferred error if KLayout density errors (metric: klayout__density_error__count) are >= 0. Doesn’t raise an error depending on error_on_var if defined.

Configuration Variables¶

Variable Name	Type	Description	Default
`ERROR_ON_KLAYOUT_DENSITY`	bool	Checks for density violations after KLayout density check is executed and exits the flow if any was found.	`True`

Layout vs. Schematic Error Checker¶

Raises a deferred error if LVS errors (metric: design__lvs_error__count) are >= 0. Doesn’t raise an error depending on error_on_var if defined.

Configuration Variables¶

Variable Name	Type	Description	Default
`ERROR_ON_LVS_ERROR` Deprecated names `QUIT_ON_LVS_ERROR`	bool	Checks for LVS errors after Netgen is executed. If any exist, it raises an error at the end of the flow.	`True`

Lint Errors Checker¶

Raises an immediate error if Lint errors (metric: design__lint_error__count) are >= 0. Doesn’t raise an error depending on error_on_var if defined.

Configuration Variables¶

Variable Name	Type	Description	Default
`ERROR_ON_LINTER_ERRORS` Deprecated names `QUIT_ON_VERILATOR_ERRORS` `QUIT_ON_LINTER_ERRORS`	bool	Quit immediately on any linter errors.	`True`

Lint Timing Errors Checker¶

Raises an immediate error if Lint Timing Errors (metric: design__lint_timing_construct__count) are >= 0. Doesn’t raise an error depending on error_on_var if defined.

Configuration Variables¶

Variable Name	Type	Description	Default
`ERROR_ON_LINTER_TIMING_CONSTRUCTS` Deprecated names `QUIT_ON_LINTER_TIMING_CONSTRUCTS`	bool	Quit immediately on any discovered timing constructs during linting.	`True`

Lint Warnings Checker¶

Raises an immediate error if Lint warnings (metric: design__lint_warning__count) are >= 0. Doesn’t raise an error depending on error_on_var if defined.

Configuration Variables¶

Variable Name	Type	Description	Default
`ERROR_ON_LINTER_WARNINGS` Deprecated names `QUIT_ON_VERILATOR_WARNINGS` `QUIT_ON_LINTER_WARNINGS`	bool	Raise an error immediately on any linter warnings.	`False`

Magic Design Rule Checker¶

Raises a deferred error if Magic DRC errors (metric: magic__drc_error__count) are >= 0. Doesn’t raise an error depending on error_on_var if defined.

Configuration Variables¶

Variable Name	Type	Description	Default
`ERROR_ON_MAGIC_DRC` Deprecated names `QUIT_ON_MAGIC_DRC`	bool	Checks for DRC violations after magic DRC is executed and exits the flow if any was found.	`True`

Maximum Capacitance Violations Checker¶

Raises a deferred error if NotImplemented (metric: design__max_cap_violation__count) are >= 0. Doesn’t raise an error depending on error_on_var if defined.

Configuration Variables¶

Variable Name	Type	Description	Default
`TIMING_VIOLATION_CORNERS` ^PDK Deprecated names `TIMING_VIOLATIONS_CORNERS`	List[str]	A list of wildcards matching IPVT corners to use during checking for timing violations.	`None`
`MAX_CAP_VIOLATION_CORNERS` ^PDK	List[str]?	A list of wildcards matching IPVT corners to use during checking for max cap violations.	`['']`

Maximum Slew Violations Checker¶

Raises a deferred error if NotImplemented (metric: design__max_slew_violation__count) are >= 0. Doesn’t raise an error depending on error_on_var if defined.

Configuration Variables¶

Variable Name	Type	Description	Default
`TIMING_VIOLATION_CORNERS` ^PDK Deprecated names `TIMING_VIOLATIONS_CORNERS`	List[str]	A list of wildcards matching IPVT corners to use during checking for timing violations.	`None`
`MAX_SLEW_VIOLATION_CORNERS` ^PDK	List[str]?	A list of wildcards matching IPVT corners to use during checking for max slew violations.	`['']`

Netlist Assign Statement Checker¶

Raises a StepError if the Netlist has an assign statement in it.

assign statements are known to cause bugs in some PnR tools.

Inputs and Outputs¶

Inputs	Outputs
nl (.nl.v)

Configuration Variables¶

Variable Name	Type	Description	Default
`ERROR_ON_NL_ASSIGN_STATEMENTS`	bool	Whether to emit an error or simply warn about the existence	`True`

Power Grid Violation Checker¶

Raises a deferred error if power grid violations (as reported by OpenROAD PSM- you may ignore these if LVS passes) (metric: design__power_grid_violation__count) are >= 0. Doesn’t raise an error depending on error_on_var if defined.

Configuration Variables¶

Variable Name	Type	Description	Default
`ERROR_ON_PDN_VIOLATIONS` Deprecated names `QUIT_ON_PDN_VIOLATIONS` `FP_PDN_CHECK_NODES`	bool	Checks for unconnected nodes in the power grid. If any exists, an error is raised at the end of the flow.	`True`

Setup Timing Violations Checker¶

Raises a deferred error if NotImplemented (metric: timing__setup_vio__count) are >= 0. Doesn’t raise an error depending on error_on_var if defined.

Configuration Variables¶

Variable Name	Type	Description	Default
`TIMING_VIOLATION_CORNERS` ^PDK Deprecated names `TIMING_VIOLATIONS_CORNERS`	List[str]	A list of wildcards matching IPVT corners to use during checking for timing violations.	`None`
`SETUP_VIOLATION_CORNERS` ^PDK	List[str]?	A list of wildcards matching IPVT corners to use during checking for setup violations.	`None`

Routing Design Rule Checker¶

Raises a deferred error if Routing DRC errors (metric: route__drc_errors) are >= 0. Doesn’t raise an error depending on error_on_var if defined.

Configuration Variables¶

Variable Name	Type	Description	Default
`ERROR_ON_TR_DRC` Deprecated names `QUIT_ON_TR_DRC`	bool	Checks for DRC violations after routing and exits the flow if any was found.	`True`

Wire Length Threshold Checker¶

Raises a deferred error if Threshold-surpassing long wires (metric: route__wirelength__max) are >= the threshold specified in the configuration file.. Doesn’t raise an error depending on error_on_var if defined.

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`ERROR_ON_LONG_WIRE` Deprecated names `QUIT_ON_LONG_WIRE`	bool	Checks if any wire length exceeds the threshold set in the PDK. If so, an error is raised at the end of the flow.	`True`
`WIRE_LENGTH_THRESHOLD` ^PDK	Decimal?	A value above which wire lengths generate warnings.	`None`	µm

Magic vs. KLayout XOR Difference Checker¶

Raises a deferred error if XOR differences (metric: design__xor_difference__count) are >= 0. Doesn’t raise an error depending on error_on_var if defined.

Configuration Variables¶

Variable Name	Type	Description	Default
`ERROR_ON_XOR_ERROR` Deprecated names `QUIT_ON_XOR_ERROR`	bool	Checks for geometric differences between the Magic and KLayout stream-outs. If any exist, raise an error at the end of the flow.	`True`

Yosys Synth Checks¶

Raises an immediate error if Yosys check errors (metric: synthesis__check_error__count) are >= 0. Doesn’t raise an error depending on error_on_var if defined.

Configuration Variables¶

Variable Name	Type	Description	Default
`ERROR_ON_SYNTH_CHECKS` Deprecated names `QUIT_ON_SYNTH_CHECKS`	bool	Quits the flow immediately if one or more synthesis check errors are flagged. This checks for combinational loops and/or wires with no drivers.	`True`

Unmapped Cells Checker¶

Raises an immediate error if Unmapped Yosys instances (metric: design__instance_unmapped__count) are >= 0. Doesn’t raise an error depending on error_on_var if defined.

Configuration Variables¶

Variable Name	Type	Description	Default
`ERROR_ON_UNMAPPED_CELLS` Deprecated names `QUIT_ON_UNMAPPED_CELLS` `CHECK_UNMAPPED_CELLS`	bool	Checks for unmapped cells after synthesis and quits immediately if so.	`True`

KLayout¶

Antenna Check¶

Runs the antenna check on the GDS.

Inputs and Outputs¶

Inputs	Outputs
gds (.gds)

Configuration Variables¶

Variable Name	Type	Description	Default
`KLAYOUT_TECH` ^PDK	Path	A path to the KLayout layer technology (.lyt) file.	`None`
`KLAYOUT_PROPERTIES` ^PDK	Path	A path to the KLayout layer properties (.lyp) file.	`None`
`KLAYOUT_DEF_LAYER_MAP` ^PDK	Path	A path to the KLayout LEF/DEF layer mapping (.map) file.	`None`
`KLAYOUT_ANTENNA_RUNSET` ^PDK	Path?	A path to KLayout antenna runset.	`None`
`KLAYOUT_ANTENNA_OPTIONS` ^PDK	Dict[str, (bool｜int｜str)]?	Options passed directly to the KLayout density runset. They vary from one PDK to another.	`None`

Design Rule Check (KLayout)¶

Runs DRC using KLayout.

Unlike most steps, the KLayout scripts vary quite wildly by PDK. If a PDK is not supported by this step, it will simply be skipped.

Currently, only sky130A and sky130B are supported.

Inputs and Outputs¶

Inputs	Outputs
gds (.gds)

Configuration Variables¶

Variable Name	Type	Description	Default
`KLAYOUT_TECH` ^PDK	Path	A path to the KLayout layer technology (.lyt) file.	`None`
`KLAYOUT_PROPERTIES` ^PDK	Path	A path to the KLayout layer properties (.lyp) file.	`None`
`KLAYOUT_DEF_LAYER_MAP` ^PDK	Path	A path to the KLayout LEF/DEF layer mapping (.map) file.	`None`
`KLAYOUT_DRC_RUNSET` ^PDK Deprecated names `KLAYOUT_DRC_TECH_SCRIPT`	Path?	A path to KLayout DRC runset.	`None`
`KLAYOUT_DRC_OPTIONS` ^PDK	Dict[str, (bool｜int｜str)]?	Options passed directly to the KLayout DRC runset. They vary from one PDK to another.	`None`
`KLAYOUT_DRC_THREADS`	int?	Specifies the number of threads to be used in KLayout DRC.If unset, this will be equal to your machine’s thread count.	`None`

Density Check¶

Runs the density check on the GDS.

Inputs and Outputs¶

Inputs	Outputs
gds (.gds)

Configuration Variables¶

Variable Name	Type	Description	Default
`KLAYOUT_TECH` ^PDK	Path	A path to the KLayout layer technology (.lyt) file.	`None`
`KLAYOUT_PROPERTIES` ^PDK	Path	A path to the KLayout layer properties (.lyp) file.	`None`
`KLAYOUT_DEF_LAYER_MAP` ^PDK	Path	A path to the KLayout LEF/DEF layer mapping (.map) file.	`None`
`KLAYOUT_DENSITY_RUNSET` ^PDK	Path?	A path to KLayout density runset.	`None`
`KLAYOUT_DENSITY_OPTIONS` ^PDK	Dict[str, (bool｜int｜str)]?	Options passed directly to the KLayout density runset. They vary from one PDK to another.	`None`
`KLAYOUT_DENSITY_THREADS`	int?	Specifies the number of threads to be used in KLayout density check.If unset, this will be equal to your machine’s thread count.	`None`

Filler Generation¶

Generates the filler cells according to the design rules and adds them to the GDS.

Inputs and Outputs¶

Inputs	Outputs
gds (.gds)	GDSII Stream (.gds)

Configuration Variables¶

Variable Name	Type	Description	Default
`KLAYOUT_TECH` ^PDK	Path	A path to the KLayout layer technology (.lyt) file.	`None`
`KLAYOUT_PROPERTIES` ^PDK	Path	A path to the KLayout layer properties (.lyp) file.	`None`
`KLAYOUT_DEF_LAYER_MAP` ^PDK	Path	A path to the KLayout LEF/DEF layer mapping (.map) file.	`None`
`KLAYOUT_FILLER_SCRIPT` ^PDK	Path?	A path to KLayout filler script.	`None`
`KLAYOUT_FILLER_OPTIONS` ^PDK	Dict[str, (bool｜int｜str)]?	Options passed directly to the KLayout filler script. They vary from one PDK to another.	`None`

Open In GUI¶

Opens the DEF view in the KLayout GUI, with layers loaded and mapped properly. Useful to inspect .klayout.xml database files and the like.

Inputs and Outputs¶

Inputs	Outputs
def (.def)

Configuration Variables¶

Variable Name	Type	Description	Default
`KLAYOUT_TECH` ^PDK	Path	A path to the KLayout layer technology (.lyt) file.	`None`
`KLAYOUT_PROPERTIES` ^PDK	Path	A path to the KLayout layer properties (.lyp) file.	`None`
`KLAYOUT_DEF_LAYER_MAP` ^PDK	Path	A path to the KLayout LEF/DEF layer mapping (.map) file.	`None`
`KLAYOUT_EDITOR_MODE`	bool	Whether to run the KLayout GUI in editor mode or in viewer mode.	`False`
`KLAYOUT_GUI_USE_GDS` Deprecated names `KLAYOUT_PRIORITIZE_GDS`	bool	Whether to prioritize GDS (if found) when running this step.	`True`

Render Image (w/ KLayout)¶

Renders a PNG of the layout using KLayout.

DEF is required as an input, but if a GDS-II view exists in the input state, it will be used instead.

Inputs and Outputs¶

Inputs	Outputs
def (.def)

Configuration Variables¶

Variable Name	Type	Description	Default
`KLAYOUT_TECH` ^PDK	Path	A path to the KLayout layer technology (.lyt) file.	`None`
`KLAYOUT_PROPERTIES` ^PDK	Path	A path to the KLayout layer properties (.lyp) file.	`None`
`KLAYOUT_DEF_LAYER_MAP` ^PDK	Path	A path to the KLayout LEF/DEF layer mapping (.map) file.	`None`
`KLAYOUT_RENDER_GRID_VISBLE`	bool	Render the grid in the image.	`False`
`KLAYOUT_RENDER_SHOW_RULER`	bool	Enable the ruler in the image.	`False`
`KLAYOUT_RENDER_BACKGROUND_COLOR`	‘white’｜ ’black’	The background color of the image.	`white`
`KLAYOUT_RENDER_TEXT_VISIBLE`	bool	Enable text in the image.	`False`
`KLAYOUT_RENDER_RESOLUTION`	int	The horizontal resolution of the image in pixel.	`1000`
`KLAYOUT_RENDER_OVERSAMPLING`	int	The oversampling factor (1..3), or 0 for disabling oversampling.	`0`

Seal Ring Generation¶

Adds a seal ring in the correct size to the GDS.

Inputs and Outputs¶

Inputs	Outputs
gds (.gds)	GDSII Stream (.gds)

Configuration Variables¶

Variable Name	Type	Description	Default
`KLAYOUT_TECH` ^PDK	Path	A path to the KLayout layer technology (.lyt) file.	`None`
`KLAYOUT_PROPERTIES` ^PDK	Path	A path to the KLayout layer properties (.lyp) file.	`None`
`KLAYOUT_DEF_LAYER_MAP` ^PDK	Path	A path to the KLayout LEF/DEF layer mapping (.map) file.	`None`
`KLAYOUT_SEALRING_SCRIPT` ^PDK	Path?	A path to KLayout seal ring script.	`None`

GDSII Stream Out (KLayout)¶

Converts DEF views into GDSII streams using KLayout.

The PDK must support KLayout for this step to work, otherwise it will be skipped.

If PRIMARY_GDSII_STREAMOUT_TOOL is set to "klayout", both GDS and KLAYOUT_GDS will be updated, and if set to another tool, only KLAYOUT_GDS will be updated.

Inputs and Outputs¶

Inputs	Outputs
def (.def)	GDSII Stream (.gds)
	GDSII Stream (KLayout) (.klayout.gds)

Configuration Variables¶

Variable Name	Type	Description	Default
`KLAYOUT_TECH` ^PDK	Path	A path to the KLayout layer technology (.lyt) file.	`None`
`KLAYOUT_PROPERTIES` ^PDK	Path	A path to the KLayout layer properties (.lyp) file.	`None`
`KLAYOUT_DEF_LAYER_MAP` ^PDK	Path	A path to the KLayout LEF/DEF layer mapping (.map) file.	`None`
`KLAYOUT_CONFLICT_RESOLUTION`	‘AddToCell’｜ ’OverwriteCell’｜ ’RenameCell’｜ ’SkipNewCell’	Specifies the conflict resolution if a cell name conflict arises.	`RenameCell`

KLayout vs. Magic XOR¶

Performs an XOR operation on the Magic and KLayout GDS views. The idea is: if there’s any difference between the GDSII streams between the two tools, one of them have it wrong and that may lead to ambiguity.

Inputs and Outputs¶

Inputs	Outputs
mag_gds (.magic.gds)
klayout_gds (.klayout.gds)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`KLAYOUT_TECH` ^PDK	Path	A path to the KLayout layer technology (.lyt) file.	`None`
`KLAYOUT_PROPERTIES` ^PDK	Path	A path to the KLayout layer properties (.lyp) file.	`None`
`KLAYOUT_DEF_LAYER_MAP` ^PDK	Path	A path to the KLayout LEF/DEF layer mapping (.map) file.	`None`
`KLAYOUT_XOR_THREADS`	int?	Specifies number of threads used in the KLayout XOR check. If unset, this will be equal to your machine’s thread count.	`None`
`KLAYOUT_XOR_IGNORE_LAYERS` ^PDK	List[str]?	KLayout layers to ignore during XOR operations.	`None`
`KLAYOUT_XOR_TILE_SIZE` ^PDK	int?	The tile size to parallelize the XOR process with.	`None`	µm

Magic¶

Design Rule Checks¶

Performs design rule checking on the GDSII stream using Magic.

This also converts the results to a KLayout database, which can be loaded.

The metrics will be updated with magic__drc_error__count. You can use the relevant checker to quit if that number is nonzero.

Inputs and Outputs¶

Inputs	Outputs
def? (.def)
gds (.gds)

Configuration Variables¶

Variable Name	Type	Description	Default
`MAGIC_DEF_LABELS`	bool	A flag to choose whether labels are read with DEF files or not. From magic docs: “The ‘-labels’ option to the ‘def read’ command causes each net in the NETS and SPECIALNETS sections of the DEF file to be annotated with a label having the net name as the label text.” If LVS fails, try disabling this option.	`False`
`MAGIC_GDS_POLYGON_SUBCELLS`	bool	A flag to enable polygon subcells in magic for gds read potentially speeding up magic. From magic docs: “Put non-Manhattan polygons. This prevents interations with other polygons on the same plane and so reduces tile splitting.”	`False`
`MAGIC_GDS_MERGE`	bool	A flag to enable merging of connected tiles into polygons during gds write. From magic docs: “Depending on the tile geometry, this may make the output file up to four times smaller, at the cost of speed in generating the output file.”	`True`
`MAGIC_DEF_NO_BLOCKAGES`	bool	If set to true, blockages in DEF files are ignored. Otherwise, they are read as sheets of metal by Magic.	`True`
`MAGIC_INCLUDE_GDS_POINTERS`	bool	A flag to choose whether to include GDS pointers in the generated mag files or not.	`False`
`MAGICRC` ^PDK Deprecated names `MAGIC_MAGICRC`	Path	A path to the `.magicrc` file which is sourced before running magic in the flow.	`None`
`MAGIC_TECH` ^PDK Deprecated names `MAGIC_TECH_FILE`	Path	A path to a Magic tech file which, mainly, has DRC rules.	`None`
`MAGIC_PDK_SETUP` ^PDK	Path	A path to a PDK-specific setup file sourced by `.magicrc`.	`None`
`CELL_MAGS` ^PDK	List[Path]?	A list of pre-processed concrete views for cells. Read as a fallback for undefined cells.	`None`
`CELL_MAGLEFS` ^PDK	List[Path]?	A list of pre-processed abstract LEF views for cells. Read as a fallback for undefined cells in scripts where cells are black-boxed.	`None`
`MAGIC_CAPTURE_ERRORS`	bool	Capture errors print by Magic and quit when a fatal error is encountered. Fatal errors are determined heuristically. It is not guaranteed that they are fatal errors. Hence this is function is gated by a variable. This function is needed because Magic does not throw errors.	`True`
`MAGIC_DRC_USE_GDS`	bool	A flag to choose whether to run the Magic DRC checks on GDS or not. If not, then the checks will be done on the DEF view of the design, which is a bit faster, but may be less accurate as some DEF/LEF elements are abstract.	`True`
`MAGIC_GDS_FLATGLOB`	List[str]?	Flatten cells by name pattern on input. May be used to avoid false positive DRC errors. The strings may use standard shell-type glob patterns, with * for any length string match, ? for any single character match, \ for special characters, and [] for matching character sets or ranges.	`None`
`MAGIC_DRC_MAGLEFS`	List[Path]?	A list of pre-processed abstract LEF views for cells. They are read in before the design and act as blackboxes during DRC.	`None`

Filler Generation¶

Generates the filler cells according to the design rules and adds them to the GDS.

Inputs and Outputs¶

Inputs	Outputs
gds (.gds)	GDSII Stream (.gds)

Configuration Variables¶

Variable Name	Type	Description	Default
`MAGIC_FILLER_SCRIPT` ^PDK	Path?	Path to the magic filler script.	`None`
`MAGIC_FILLER_OPTIONS` ^PDK	List[str]?	Options passed directly to the magic filler script.	`None`

Open In GUI¶

Opens the DEF view in the Magic GUI.

Inputs and Outputs¶

Inputs	Outputs
def (.def)

Configuration Variables¶

Variable Name	Type	Description	Default
`MAGIC_DEF_LABELS`	bool	A flag to choose whether labels are read with DEF files or not. From magic docs: “The ‘-labels’ option to the ‘def read’ command causes each net in the NETS and SPECIALNETS sections of the DEF file to be annotated with a label having the net name as the label text.” If LVS fails, try disabling this option.	`False`
`MAGIC_GDS_POLYGON_SUBCELLS`	bool	A flag to enable polygon subcells in magic for gds read potentially speeding up magic. From magic docs: “Put non-Manhattan polygons. This prevents interations with other polygons on the same plane and so reduces tile splitting.”	`False`
`MAGIC_GDS_MERGE`	bool	A flag to enable merging of connected tiles into polygons during gds write. From magic docs: “Depending on the tile geometry, this may make the output file up to four times smaller, at the cost of speed in generating the output file.”	`True`
`MAGIC_DEF_NO_BLOCKAGES`	bool	If set to true, blockages in DEF files are ignored. Otherwise, they are read as sheets of metal by Magic.	`True`
`MAGIC_INCLUDE_GDS_POINTERS`	bool	A flag to choose whether to include GDS pointers in the generated mag files or not.	`False`
`MAGICRC` ^PDK Deprecated names `MAGIC_MAGICRC`	Path	A path to the `.magicrc` file which is sourced before running magic in the flow.	`None`
`MAGIC_TECH` ^PDK Deprecated names `MAGIC_TECH_FILE`	Path	A path to a Magic tech file which, mainly, has DRC rules.	`None`
`MAGIC_PDK_SETUP` ^PDK	Path	A path to a PDK-specific setup file sourced by `.magicrc`.	`None`
`CELL_MAGS` ^PDK	List[Path]?	A list of pre-processed concrete views for cells. Read as a fallback for undefined cells.	`None`
`CELL_MAGLEFS` ^PDK	List[Path]?	A list of pre-processed abstract LEF views for cells. Read as a fallback for undefined cells in scripts where cells are black-boxed.	`None`
`MAGIC_CAPTURE_ERRORS`	bool	Capture errors print by Magic and quit when a fatal error is encountered. Fatal errors are determined heuristically. It is not guaranteed that they are fatal errors. Hence this is function is gated by a variable. This function is needed because Magic does not throw errors.	`True`
`MAGIC_GUI_USE_GDS`	bool	Whether to prioritize GDS (if found) when running this step.	`True`

Full Parasitics Extraction¶

Performs a full parasitics extraction (RCX) using Magic. This step is suitable for performing full analogue post-layout simulation of your design. The SPICE netlist will be flattened, and refer to the raw n-type/p-type transistor models for your PDK.

If you want to do device level simulation without parasitics, this can be done in the Magic.SpiceExtraction step by setting MAGIC_EXT_USE_GDS to True and MAGIC_EXT_ABSTRACT to False.

Inputs and Outputs¶

Inputs	Outputs
gds (.gds)	Simulation Program with Integrated Circuit Emphasis (with Resistance and Capacitance eXtraction) (.rcx.spice)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`MAGIC_DEF_LABELS`	bool	A flag to choose whether labels are read with DEF files or not. From magic docs: “The ‘-labels’ option to the ‘def read’ command causes each net in the NETS and SPECIALNETS sections of the DEF file to be annotated with a label having the net name as the label text.” If LVS fails, try disabling this option.	`False`
`MAGIC_GDS_POLYGON_SUBCELLS`	bool	A flag to enable polygon subcells in magic for gds read potentially speeding up magic. From magic docs: “Put non-Manhattan polygons. This prevents interations with other polygons on the same plane and so reduces tile splitting.”	`False`
`MAGIC_GDS_MERGE`	bool	A flag to enable merging of connected tiles into polygons during gds write. From magic docs: “Depending on the tile geometry, this may make the output file up to four times smaller, at the cost of speed in generating the output file.”	`True`
`MAGIC_DEF_NO_BLOCKAGES`	bool	If set to true, blockages in DEF files are ignored. Otherwise, they are read as sheets of metal by Magic.	`True`
`MAGIC_INCLUDE_GDS_POINTERS`	bool	A flag to choose whether to include GDS pointers in the generated mag files or not.	`False`
`MAGICRC` ^PDK Deprecated names `MAGIC_MAGICRC`	Path	A path to the `.magicrc` file which is sourced before running magic in the flow.	`None`
`MAGIC_TECH` ^PDK Deprecated names `MAGIC_TECH_FILE`	Path	A path to a Magic tech file which, mainly, has DRC rules.	`None`
`MAGIC_PDK_SETUP` ^PDK	Path	A path to a PDK-specific setup file sourced by `.magicrc`.	`None`
`CELL_MAGS` ^PDK	List[Path]?	A list of pre-processed concrete views for cells. Read as a fallback for undefined cells.	`None`
`CELL_MAGLEFS` ^PDK	List[Path]?	A list of pre-processed abstract LEF views for cells. Read as a fallback for undefined cells in scripts where cells are black-boxed.	`None`
`MAGIC_CAPTURE_ERRORS`	bool	Capture errors print by Magic and quit when a fatal error is encountered. Fatal errors are determined heuristically. It is not guaranteed that they are fatal errors. Hence this is function is gated by a variable. This function is needed because Magic does not throw errors.	`True`
`MAGIC_RCX_CTHRESH`	float	Capacitance threshold value.	`0.1`	femtofarads
`MAGIC_RCX_DO_CAPACITANCE`	bool	Whether to extract local capacitance values.	`True`
`MAGIC_RCX_DO_RESISTANCE`	bool	Whether to perform detailed (i.e. non-lumped) resistance extraction.	`True`
`MAGIC_RCX_EXTRACT_STYLE`	str	Capacitance extraction corner. For open PDKs, the options are generally: ‘ngspice(lrlc)’, low resistance, low capacitance; ‘ngspice(hrlc)’, high resistance, low capacitance; ‘ngspice(lrhc)’, low resistance, high capacitance; ‘ngspice(hrhc)’, high resistance, low capacitance. ‘ngspice(hrhc)’ is typically the slowest corner, and ‘ngspice(lrlc) is typically the fastest corner. Defaults to ‘ngspice()’, which is the default typical extraction corner.	`ngspice()`

SPICE Model Extraction¶

Extracts a SPICE netlist from the GDSII stream. Used in Layout vs. Schematic checks.

Note that the resultant SPICE netlist is blackboxed, and only suitable for abstract LVS. If you want to perform a full parasitics extraction (RCX), you should use the Magic.RCX step.

Also, the metrics will be updated with magic__illegal_overlap__count. You can use the relevant checker to quit if that number is nonzero.

Inputs and Outputs¶

Inputs	Outputs
gds (.gds)	Simulation Program with Integrated Circuit Emphasis (.spice)
def (.def)

Configuration Variables¶

Variable Name	Type	Description	Default
`MAGIC_DEF_LABELS`	bool	A flag to choose whether labels are read with DEF files or not. From magic docs: “The ‘-labels’ option to the ‘def read’ command causes each net in the NETS and SPECIALNETS sections of the DEF file to be annotated with a label having the net name as the label text.” If LVS fails, try disabling this option.	`False`
`MAGIC_GDS_POLYGON_SUBCELLS`	bool	A flag to enable polygon subcells in magic for gds read potentially speeding up magic. From magic docs: “Put non-Manhattan polygons. This prevents interations with other polygons on the same plane and so reduces tile splitting.”	`False`
`MAGIC_GDS_MERGE`	bool	A flag to enable merging of connected tiles into polygons during gds write. From magic docs: “Depending on the tile geometry, this may make the output file up to four times smaller, at the cost of speed in generating the output file.”	`True`
`MAGIC_DEF_NO_BLOCKAGES`	bool	If set to true, blockages in DEF files are ignored. Otherwise, they are read as sheets of metal by Magic.	`True`
`MAGIC_INCLUDE_GDS_POINTERS`	bool	A flag to choose whether to include GDS pointers in the generated mag files or not.	`False`
`MAGICRC` ^PDK Deprecated names `MAGIC_MAGICRC`	Path	A path to the `.magicrc` file which is sourced before running magic in the flow.	`None`
`MAGIC_TECH` ^PDK Deprecated names `MAGIC_TECH_FILE`	Path	A path to a Magic tech file which, mainly, has DRC rules.	`None`
`MAGIC_PDK_SETUP` ^PDK	Path	A path to a PDK-specific setup file sourced by `.magicrc`.	`None`
`CELL_MAGS` ^PDK	List[Path]?	A list of pre-processed concrete views for cells. Read as a fallback for undefined cells.	`None`
`CELL_MAGLEFS` ^PDK	List[Path]?	A list of pre-processed abstract LEF views for cells. Read as a fallback for undefined cells in scripts where cells are black-boxed.	`None`
`MAGIC_CAPTURE_ERRORS`	bool	Capture errors print by Magic and quit when a fatal error is encountered. Fatal errors are determined heuristically. It is not guaranteed that they are fatal errors. Hence this is function is gated by a variable. This function is needed because Magic does not throw errors.	`True`
`MAGIC_EXT_USE_GDS`	bool	A flag to choose whether to use GDS for spice extraction or not. If not, then the extraction will be done using the DEF/LEF, which is faster.	`False`
`MAGIC_EXT_ABSTRACT_CELLS`	List[str]?	A list of regular expressions which are matched against the cells of a the design. Matches are abstracted (black-boxed) during SPICE extraction.	`None`
`MAGIC_EXT_UNIQUE` Deprecated names `MAGIC_NO_EXT_UNIQUE` `LVS_CONNECT_BY_LABEL`	‘all’｜ ’notopports’｜ ’noports’｜ ’none’	Runs `extract unique` with the specified option. The default is “all”, and “none” disables `extract unique`, allowing connections between separate nets by label in LVS.	`all`
`MAGIC_EXT_SHORT_RESISTOR`	bool	Enables adding resistors to shorts- resolves LVS issues if more than one top-level pin is connected to the same net, but may increase runtime and break some designs. Proceed with caution.	`False`
`MAGIC_EXT_ABSTRACT`	bool	Extracts a SPICE netlist based on black-boxed standard cells and macros (basically, anything with a LEF) rather than transistors. An error will be thrown if both this and `MAGIC_EXT_USE_GDS` is set to `True`.	`False`
`MAGIC_FEEDBACK_CONVERSION_THRESHOLD`	int	If Magic provides more feedback items than this threshold, conversion to KLayout databases is skipped (as something has gone horribly wrong.)	`10000`

GDSII Stream Out (Magic)¶

Converts DEF views into GDSII streams using Magic.

If PRIMARY_GDSII_STREAMOUT_TOOL is set to "magic", both GDS and MAG_GDS will be updated, and if set to another tool, only MAG_GDS will be updated.

Inputs and Outputs¶

Inputs	Outputs
def (.def)	GDSII Stream (.gds)
	GDSII Stream (Magic) (.magic.gds)
	Magic VLSI View (.mag)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`MAGIC_DEF_LABELS`	bool	A flag to choose whether labels are read with DEF files or not. From magic docs: “The ‘-labels’ option to the ‘def read’ command causes each net in the NETS and SPECIALNETS sections of the DEF file to be annotated with a label having the net name as the label text.” If LVS fails, try disabling this option.	`False`
`MAGIC_GDS_POLYGON_SUBCELLS`	bool	A flag to enable polygon subcells in magic for gds read potentially speeding up magic. From magic docs: “Put non-Manhattan polygons. This prevents interations with other polygons on the same plane and so reduces tile splitting.”	`False`
`MAGIC_GDS_MERGE`	bool	A flag to enable merging of connected tiles into polygons during gds write. From magic docs: “Depending on the tile geometry, this may make the output file up to four times smaller, at the cost of speed in generating the output file.”	`True`
`MAGIC_DEF_NO_BLOCKAGES`	bool	If set to true, blockages in DEF files are ignored. Otherwise, they are read as sheets of metal by Magic.	`True`
`MAGIC_INCLUDE_GDS_POINTERS`	bool	A flag to choose whether to include GDS pointers in the generated mag files or not.	`False`
`MAGICRC` ^PDK Deprecated names `MAGIC_MAGICRC`	Path	A path to the `.magicrc` file which is sourced before running magic in the flow.	`None`
`MAGIC_TECH` ^PDK Deprecated names `MAGIC_TECH_FILE`	Path	A path to a Magic tech file which, mainly, has DRC rules.	`None`
`MAGIC_PDK_SETUP` ^PDK	Path	A path to a PDK-specific setup file sourced by `.magicrc`.	`None`
`CELL_MAGS` ^PDK	List[Path]?	A list of pre-processed concrete views for cells. Read as a fallback for undefined cells.	`None`
`CELL_MAGLEFS` ^PDK	List[Path]?	A list of pre-processed abstract LEF views for cells. Read as a fallback for undefined cells in scripts where cells are black-boxed.	`None`
`MAGIC_CAPTURE_ERRORS`	bool	Capture errors print by Magic and quit when a fatal error is encountered. Fatal errors are determined heuristically. It is not guaranteed that they are fatal errors. Hence this is function is gated by a variable. This function is needed because Magic does not throw errors.	`True`
`DIE_AREA`	Tuple[Decimal, Decimal, Decimal, Decimal]?	Specific die area to be used in floorplanning when `FP_SIZING` is set to `absolute`. Specified as a 4-corner rectangle “x0 y0 x1 y1”.	`None`	µm
`MAGIC_ZEROIZE_ORIGIN`	bool	A flag to move the layout such that it’s origin in the lef generated by magic is 0,0.	`False`
`MAGIC_DISABLE_CIF_INFO` Deprecated names `MAGIC_DISABLE_HIER_GDS`	bool	A flag to disable writing Caltech Intermediate Format (CIF) hierarchy and subcell array information to the GDSII file.	`True`
`MAGIC_MACRO_STD_CELL_SOURCE`	‘PDK’｜ ’macro’	If set to PDK, magic will use the PDK definition of the STD cells for macros inside the design. Otherwise, the macro is completely treated as a blackbox and magic will use the existing cell definition inside the macro gds. This mode is only supported for macros specified in MACROS variable	`macro`

Write LEF (Magic)¶

Writes a LEF view of the design using the GDS using Magic.

Inputs and Outputs¶

Inputs	Outputs
gds (.gds)	Library Exchange Format (.lef)
def (.def)

Configuration Variables¶

Variable Name	Type	Description	Default
`MAGIC_DEF_LABELS`	bool	A flag to choose whether labels are read with DEF files or not. From magic docs: “The ‘-labels’ option to the ‘def read’ command causes each net in the NETS and SPECIALNETS sections of the DEF file to be annotated with a label having the net name as the label text.” If LVS fails, try disabling this option.	`False`
`MAGIC_GDS_POLYGON_SUBCELLS`	bool	A flag to enable polygon subcells in magic for gds read potentially speeding up magic. From magic docs: “Put non-Manhattan polygons. This prevents interations with other polygons on the same plane and so reduces tile splitting.”	`False`
`MAGIC_GDS_MERGE`	bool	A flag to enable merging of connected tiles into polygons during gds write. From magic docs: “Depending on the tile geometry, this may make the output file up to four times smaller, at the cost of speed in generating the output file.”	`True`
`MAGIC_DEF_NO_BLOCKAGES`	bool	If set to true, blockages in DEF files are ignored. Otherwise, they are read as sheets of metal by Magic.	`True`
`MAGIC_INCLUDE_GDS_POINTERS`	bool	A flag to choose whether to include GDS pointers in the generated mag files or not.	`False`
`MAGICRC` ^PDK Deprecated names `MAGIC_MAGICRC`	Path	A path to the `.magicrc` file which is sourced before running magic in the flow.	`None`
`MAGIC_TECH` ^PDK Deprecated names `MAGIC_TECH_FILE`	Path	A path to a Magic tech file which, mainly, has DRC rules.	`None`
`MAGIC_PDK_SETUP` ^PDK	Path	A path to a PDK-specific setup file sourced by `.magicrc`.	`None`
`CELL_MAGS` ^PDK	List[Path]?	A list of pre-processed concrete views for cells. Read as a fallback for undefined cells.	`None`
`CELL_MAGLEFS` ^PDK	List[Path]?	A list of pre-processed abstract LEF views for cells. Read as a fallback for undefined cells in scripts where cells are black-boxed.	`None`
`MAGIC_CAPTURE_ERRORS`	bool	Capture errors print by Magic and quit when a fatal error is encountered. Fatal errors are determined heuristically. It is not guaranteed that they are fatal errors. Hence this is function is gated by a variable. This function is needed because Magic does not throw errors.	`True`
`MAGIC_LEF_WRITE_USE_GDS`	bool	A flag to choose whether to use GDS for LEF writing. If not, then the extraction will be done using abstract LEF views.	`False`
`MAGIC_WRITE_FULL_LEF`	bool	A flag to specify whether or not the output LEF should include all shapes inside the macro or an abstracted view of the macro LEF view via magic.	`False`
`MAGIC_WRITE_LEF_PINONLY`	bool	If true, the LEF write will mark only areas that are port labels as pins, while marking the rest of each related net as an obstruction. Otherwise, the labeled port and the any connected metal on the same layer are marked as a pin.	`False`

Netgen¶

Netgen LVS¶

Performs Layout vs. Schematic checks on the extracted SPICE netlist versus. a Verilog netlist with power connections.

This verifies the following: * There are no unexpected shorts in the final layout. * There are no unexpected opens in the final layout. * All signals are connected correctly.

Inputs and Outputs¶

Inputs	Outputs
spice (.spice)
pnl (.pnl.v)

Configuration Variables¶

Variable Name	Type	Description	Default
`MAGIC_EXT_USE_GDS`	bool	A flag to choose whether to use GDS for spice extraction or not. If not, then the extraction will be done using the DEF/LEF, which is faster.	`False`
`NETGEN_SETUP` ^PDK Deprecated names `NETGEN_SETUP_FILE`	Path	A path to the setup file for Netgen used to configure LVS. If set to None, this PDK will not support Netgen-based steps.	`None`
`LVS_INCLUDE_MARCO_NETLISTS`	bool	A flag that enables including the gate-level netlist of macros while running Netgen	`False`
`LVS_FLATTEN_CELLS`	List[str]?	A list of cell names to be flattened while running LVS	`None`
`LVS_IGNORE_CELLS`	List[str]?	A list of cell names to be ignored while running LVS	`None`

Odb¶

Add PDN obstructions¶

Adds obstructions on metal layers which prevent shapes from being created in the designated areas.

A soft-duplicate of <#Odb.AddRoutingObstructions>`_ , though this one uses a different variable name so the obstructions can be restricted for PDN steps only.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`PDN_OBSTRUCTIONS`	List[Tuple[str, Decimal, Decimal, Decimal, Decimal]]?	Add routing obstructions to the design before PDN stage. If set to `None`, this step is skipped. Format of each obstruction item is a tuple of: layer name, llx, lly, urx, ury,.	`None`	µm

Add Obstructions¶

Adds obstructions on metal layers which prevent shapes from being created in the designated areas.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`ROUTING_OBSTRUCTIONS` Deprecated names `GRT_OBS`	List[Tuple[str, Decimal, Decimal, Decimal, Decimal]]?	Add routing obstructions to the design. If set to `None`, this step is skipped. Format of each obstruction item is a tuple of: layer name, llx, lly, urx, ury.	`None`	µm

Apply DEF Template¶

Copies the floorplan of a “template” DEF file for a new design, i.e., it will copy the die area, core area, and non-power pin names and locations.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)

Configuration Variables¶

Variable Name	Type	Description	Default
`FP_DEF_TEMPLATE`	Path?	Points to the DEF file to be used as a template.	`None`
`FP_TEMPLATE_MATCH_MODE`	‘strict’｜ ’permissive’	Whether to require that the pin set of the DEF template and the design should be identical. In permissive mode, pins that are in the design and not in the template will be excluded, and vice versa.	`strict`
`FP_TEMPLATE_COPY_POWER_PINS`	bool	Whether to always copy all power pins from the DEF template to the design.	`False`

Generate Cell Frequency Tables¶

Creates a number of tables to show the cell frequencies by:

Cells
Buffer cells only
Cell Function*
Standard Cell Library*

These tables only return meaningful info with PDKs distributed in the Open_PDKs format, i.e., all cells are named {scl}__{cell_fn}_{size}.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)

Check Antenna Properties of Pins in The Generated Design LEF view¶

Prints warnings if the LEF view of the design is missing antenna information.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)
lef (.lef)

Check Antenna Properties of Macros Pins in Their LEF Views¶

Prints warnings if the LEF views of macros are missing antenna information.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)

Custom I/O Pin Placement Script¶

Places I/O pins using a custom script, which uses a “pin order configuration” file.

Check the reference documentation for the structure of said file.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`IO_PIN_H_LAYER` ^PDK Deprecated names `FP_IO_HLAYER`	str	The metal layer on which to place horizontally-aligned (long side parallel with the horizon) pins alongside the east and west edges of the die.	`None`
`IO_PIN_V_LAYER` ^PDK Deprecated names `FP_IO_VLAYER`	str	The metal layer on which to place vertically-aligned (long side perpendicular to the horizon) pins alongside the north and south edges of the die.	`None`
`IO_PIN_V_EXTENSION` Deprecated names `FP_IO_VEXTEND`	Decimal	Extends the vertical io pins outside of the die by the specified units.	`0`	µm
`IO_PIN_H_EXTENSION` Deprecated names `FP_IO_HEXTEND`	Decimal	Extends the horizontal io pins outside of the die by the specified units.	`0`	µm
`IO_PIN_V_THICKNESS_MULT` Deprecated names `FP_IO_VTHICKNESS_MULT`	Decimal	A multiplier for vertical pin thickness. Base thickness is the pins layer min width.	`2`
`IO_PIN_H_THICKNESS_MULT` Deprecated names `FP_IO_HTHICKNESS_MULT`	Decimal	A multiplier for horizontal pin thickness. Base thickness is the pins layer min width.	`2`
`IO_PIN_V_LENGTH` ^PDK Deprecated names `FP_IO_VLENGTH`	Decimal?	The length of the pins with a north or south orientation. If unspecified by a PDK, OpenROAD will use whichever is higher of the following two values: * The pin width * The minimum value satisfying the minimum area constraint given the pin width	`None`	µm
`IO_PIN_H_LENGTH` ^PDK Deprecated names `FP_IO_HLENGTH`	Decimal?	The length of the pins with an east or west orientation. If unspecified by a PDK, OpenROAD will use whichever is higher of the following two values: * The pin width * The minimum value satisfying the minimum area constraint given the pin width	`None`	µm
`IO_PIN_ORDER_CFG` Deprecated names `FP_PIN_ORDER_CFG`	Path?	Path to a custom pin configuration file.	`None`
`ERRORS_ON_UNMATCHED_IO` Deprecated names `QUIT_ON_UNMATCHED_IO`	‘none’｜ ’unmatched_design’｜ ’unmatched_cfg’｜ ’both’	Controls whether to emit an error in: no situation, when pins exist in the design that do not exist in the config file, when pins exist in the config file that do not exist in the design, and both respectively. `both` is recommended, as the default is only for backwards compatibility with LibreLane 1.	`unmatched_design`

Diodes on Ports Protection Routine¶

Unconditionally inserts diodes on design ports diodes on ports, to mitigate the antenna effect.

Useful for hardening macros, where ports may get long wires that are unaccounted for when hardening a top-level chip.

The placement is legalized by performing detailed placement and global routing after inserting the diodes.

Prior to beta 16, this step did not legalize its placement: if you would like to retain the old behavior without legalization, try Odb.PortDiodePlacement.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	Design Constraints (.sdc)
	Design Exchange Format (.def)
	Powered Verilog Netlist (.pnl.v)
	OpenDB Database (.odb)
	Verilog Netlist (.nl.v)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`DIODE_ON_PORTS`	‘none’｜ ’in’｜ ’out’｜ ’both’	Always insert diodes on ports with the specified polarities.	`none`
`GPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for global placement. Used by this step only to emit a warning if it’s 0.	`None`	sites
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`PL_OPTIMIZE_MIRRORING`	bool	Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design.	`True`
`PL_MAX_DISPLACEMENT_X`	int	Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement.	`500`	µm
`PL_MAX_DISPLACEMENT_Y`	int	Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement.	`100`	µm
`DPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement.	`None`	sites
`RT_CLOCK_MIN_LAYER`	str?	The name of lowest layer to be used in routing the clock net.	`None`
`RT_CLOCK_MAX_LAYER`	str?	The name of highest layer to be used in routing the clock net.	`None`
`GRT_ADJUSTMENT`	Decimal	Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction.	`0.3`
`GRT_MACRO_EXTENSION`	int	Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches.	`0`
`GRT_LAYER_ADJUSTMENTS` ^PDK	List[Decimal]	Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1.	`None`
`DIODE_PADDING`	int?	Diode cell padding; increases the width of diode cells during placement checks..	`None`	sites
`GRT_ALLOW_CONGESTION`	bool	Allow congestion during global routing	`False`
`GRT_ANTENNA_REPAIR_ITERS` Deprecated names `GRT_ANT_ITERS` `GRT_ANTENNA_ITERS`	int	The maximum number of iterations for global antenna repairs.	`3`
`GRT_OVERFLOW_ITERS`	int	The maximum number of iterations waiting for the overflow to reach the desired value.	`50`
`GRT_ANTENNA_REPAIR_MARGIN` Deprecated names `GRT_ANT_MARGIN` `GRT_ANTENNA_MARGIN`	int	The margin to over fix antenna violations.	`10`
`GRT_ANTENNA_REPAIR_JUMPER_ONLY`	bool	Only use jumpers to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_DIODE_ONLY.	`False`
`GRT_ANTENNA_REPAIR_DIODE_ONLY`	bool	Only use antenna diodes to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_JUMPER_ONLY.	`False`

Fuzzy Diode Placement¶

Runs a custom diode placement script to mitigate the antenna effect.

This script uses the Manhattan length of a (non-existent) wire at the global placement stage, and places diodes if they exceed a certain threshold. This, however, requires some padding: GPL_CELL_PADDING and DPL_CELL_PADDING must be higher than 0 for this script to work reliably.

The placement is not legalized.

The original script was written by Sylvain “tnt” Munaut.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`HEURISTIC_ANTENNA_THRESHOLD` ^PDK	Decimal?	A Manhattan distance above which a diode is recommended to be inserted by the heuristic inserter. If not specified, the heuristic algorithm.	`None`	µm
`GPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for global placement. Used by this step only to emit a warning if it’s 0.	`None`	sites

Heuristic Diode Insertion Routine¶

Runs a custom diode insertion routine to mitigate the antenna effect.

The placement is then legalized by performing detailed placement and global routing after inserting the diodes.

The original script was written by Sylvain “tnt” Munaut.

Prior to beta 16, this step did not legalize its placement: if you would like to retain the old behavior without legalization, try Odb.FuzzyDiodePlacement.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	Design Constraints (.sdc)
	Design Exchange Format (.def)
	Powered Verilog Netlist (.pnl.v)
	OpenDB Database (.odb)
	Verilog Netlist (.nl.v)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`HEURISTIC_ANTENNA_THRESHOLD` ^PDK	Decimal?	A Manhattan distance above which a diode is recommended to be inserted by the heuristic inserter. If not specified, the heuristic algorithm.	`None`	µm
`GPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for global placement. Used by this step only to emit a warning if it’s 0.	`None`	sites
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`PL_OPTIMIZE_MIRRORING`	bool	Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design.	`True`
`PL_MAX_DISPLACEMENT_X`	int	Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement.	`500`	µm
`PL_MAX_DISPLACEMENT_Y`	int	Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement.	`100`	µm
`DPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement.	`None`	sites
`RT_CLOCK_MIN_LAYER`	str?	The name of lowest layer to be used in routing the clock net.	`None`
`RT_CLOCK_MAX_LAYER`	str?	The name of highest layer to be used in routing the clock net.	`None`
`GRT_ADJUSTMENT`	Decimal	Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction.	`0.3`
`GRT_MACRO_EXTENSION`	int	Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches.	`0`
`GRT_LAYER_ADJUSTMENTS` ^PDK	List[Decimal]	Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1.	`None`
`DIODE_PADDING`	int?	Diode cell padding; increases the width of diode cells during placement checks..	`None`	sites
`GRT_ALLOW_CONGESTION`	bool	Allow congestion during global routing	`False`
`GRT_ANTENNA_REPAIR_ITERS` Deprecated names `GRT_ANT_ITERS` `GRT_ANTENNA_ITERS`	int	The maximum number of iterations for global antenna repairs.	`3`
`GRT_OVERFLOW_ITERS`	int	The maximum number of iterations waiting for the overflow to reach the desired value.	`50`
`GRT_ANTENNA_REPAIR_MARGIN` Deprecated names `GRT_ANT_MARGIN` `GRT_ANTENNA_MARGIN`	int	The margin to over fix antenna violations.	`10`
`GRT_ANTENNA_REPAIR_JUMPER_ONLY`	bool	Only use jumpers to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_DIODE_ONLY.	`False`
`GRT_ANTENNA_REPAIR_DIODE_ONLY`	bool	Only use antenna diodes to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_JUMPER_ONLY.	`False`

Insert ECO Buffers¶

Experimental step to insert ECO buffers on either drivers or sinks after global or detailed routing. The placement is legalized and global routing is incrementally re-run for affected nets. Useful for manually fixing some hold violations.

If run after detailed routing, detailed routing must be re-run as affected nets that are altered are removed and require re-routing.

INOUT and FEEDTHRU ports are not supported.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`PL_OPTIMIZE_MIRRORING`	bool	Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design.	`True`
`PL_MAX_DISPLACEMENT_X`	int	Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement.	`500`	µm
`PL_MAX_DISPLACEMENT_Y`	int	Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement.	`100`	µm
`DPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement.	`None`	sites
`RT_CLOCK_MIN_LAYER`	str?	The name of lowest layer to be used in routing the clock net.	`None`
`RT_CLOCK_MAX_LAYER`	str?	The name of highest layer to be used in routing the clock net.	`None`
`GRT_ADJUSTMENT`	Decimal	Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction.	`0.3`
`GRT_MACRO_EXTENSION`	int	Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches.	`0`
`GRT_LAYER_ADJUSTMENTS` ^PDK	List[Decimal]	Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1.	`None`
`DIODE_PADDING`	int?	Diode cell padding; increases the width of diode cells during placement checks..	`None`	sites
`GRT_ALLOW_CONGESTION`	bool	Allow congestion during global routing	`False`
`GRT_ANTENNA_REPAIR_ITERS` Deprecated names `GRT_ANT_ITERS` `GRT_ANTENNA_ITERS`	int	The maximum number of iterations for global antenna repairs.	`3`
`GRT_OVERFLOW_ITERS`	int	The maximum number of iterations waiting for the overflow to reach the desired value.	`50`
`GRT_ANTENNA_REPAIR_MARGIN` Deprecated names `GRT_ANT_MARGIN` `GRT_ANTENNA_MARGIN`	int	The margin to over fix antenna violations.	`10`
`GRT_ANTENNA_REPAIR_JUMPER_ONLY`	bool	Only use jumpers to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_DIODE_ONLY.	`False`
`GRT_ANTENNA_REPAIR_DIODE_ONLY`	bool	Only use antenna diodes to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_JUMPER_ONLY.	`False`
`INSERT_ECO_BUFFERS`	List[`ECOBuffer`]?	List of buffers to insert	`None`

Insert ECO Diodes¶

Experimental step to create and attach ECO diodes to the nets of sinks after global or detailed routing. The placement is legalized and global routing is incrementally re-run for affected nets. Useful for manually fixing some antenna violations.

If run after detailed routing, detailed routing must be re-run as affected nets that are altered are removed and require re-routing.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`RT_CLOCK_MIN_LAYER`	str?	The name of lowest layer to be used in routing the clock net.	`None`
`RT_CLOCK_MAX_LAYER`	str?	The name of highest layer to be used in routing the clock net.	`None`
`GRT_ADJUSTMENT`	Decimal	Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction.	`0.3`
`GRT_MACRO_EXTENSION`	int	Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches.	`0`
`GRT_LAYER_ADJUSTMENTS` ^PDK	List[Decimal]	Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1.	`None`
`DIODE_PADDING`	int?	Diode cell padding; increases the width of diode cells during placement checks..	`None`	sites
`GRT_ALLOW_CONGESTION`	bool	Allow congestion during global routing	`False`
`GRT_ANTENNA_REPAIR_ITERS` Deprecated names `GRT_ANT_ITERS` `GRT_ANTENNA_ITERS`	int	The maximum number of iterations for global antenna repairs.	`3`
`GRT_OVERFLOW_ITERS`	int	The maximum number of iterations waiting for the overflow to reach the desired value.	`50`
`GRT_ANTENNA_REPAIR_MARGIN` Deprecated names `GRT_ANT_MARGIN` `GRT_ANTENNA_MARGIN`	int	The margin to over fix antenna violations.	`10`
`GRT_ANTENNA_REPAIR_JUMPER_ONLY`	bool	Only use jumpers to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_DIODE_ONLY.	`False`
`GRT_ANTENNA_REPAIR_DIODE_ONLY`	bool	Only use antenna diodes to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_JUMPER_ONLY.	`False`
`PL_OPTIMIZE_MIRRORING`	bool	Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design.	`True`
`PL_MAX_DISPLACEMENT_X`	int	Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement.	`500`	µm
`PL_MAX_DISPLACEMENT_Y`	int	Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement.	`100`	µm
`DPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement.	`None`	sites
`INSERT_ECO_DIODES`	List[`ECODiode`]?	List of sinks to insert diodes for.	`None`

Manual Global Placement¶

This is an step to override the placement of one or more instances at user-specified locations.

Alternatively, if this is a custom design with a few cells, this can be used in place of the global placement entirely.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)

Configuration Variables¶

Variable Name	Type	Description	Default
`MANUAL_GLOBAL_PLACEMENTS`	Dict[str, `Instance`]?	A dictionary of instances to their global (non-legalized and unfixed) placement location.	`None`

Manual Macro Placement¶

Performs macro placement using a simple configuration file. The file is defined as a line-break delimited list of instances and positions, in the format instance_name X_pos Y_pos Orientation.

If no macro instances are configured, this step is skipped.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)

Configuration Variables¶

Variable Name	Type	Description	Default
`MACRO_PLACEMENT_CFG`	Path?	Path to an optional override for instance placement instead of the `MACROS` object for compatibility with LibreLane 1. If both are `None`, this step is skipped.	`None`

Port Diode Placement Script¶

Unconditionally inserts diodes on design ports diodes on ports, to mitigate the antenna effect.

Useful for hardening macros, where ports may get long wires that are unaccounted for when hardening a top-level chip.

The placement is not legalized.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`DIODE_ON_PORTS`	‘none’｜ ’in’｜ ’out’｜ ’both’	Always insert diodes on ports with the specified polarities.	`none`
`GPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for global placement. Used by this step only to emit a warning if it’s 0.	`None`	sites

Remove PDN obstructions¶

Removes any PDN obstructions previously placed by <#Odb.RemovePDNObstructions>`_.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`PDN_OBSTRUCTIONS`	List[Tuple[str, Decimal, Decimal, Decimal, Decimal]]?	Add routing obstructions to the design before PDN stage. If set to `None`, this step is skipped. Format of each obstruction item is a tuple of: layer name, llx, lly, urx, ury,.	`None`	µm

Remove Obstructions¶

Removes any routing obstructions previously placed by <#Odb.AddRoutingObstructions>`_.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`ROUTING_OBSTRUCTIONS` Deprecated names `GRT_OBS`	List[Tuple[str, Decimal, Decimal, Decimal, Decimal]]?	Add routing obstructions to the design. If set to `None`, this step is skipped. Format of each obstruction item is a tuple of: layer name, llx, lly, urx, ury.	`None`	µm

Report Disconnected Pins¶

Creates a table of disconnected pins in the design, updating metrics as appropriate.

Disconnected pins may be marked “critical” if they are very likely to result in a dead design. We determine if a pin is critical as follows:

For the top-level macro: for these four kinds of pins: inputs, outputs, power inouts, and ground inouts, at least one of each kind must be connected or else all pins of a certain kind are counted as critical disconnected pins.
For instances:
- Any unconnected input is a critical disconnected pin.
- If there isn’t at least one output connected, all disconnected outputs are critical disconnected pins.
- Any disconnected power inout pins are critical disconnected pins.

The metrics design__disconnected_pin__count and design__critical_disconnected_pin__count is updated. It is recommended to use the checker Checker.DisconnectedPins to check that there are no critical disconnected pins.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)

Configuration Variables¶

Variable Name	Type	Description	Default
`IGNORE_DISCONNECTED_MODULES` ^PDK	List[str]?	Modules (or cells) to ignore when checking for disconnected pins.	`None`

Report Wire Length¶

Outputs a CSV of long wires, printed by length. Useful as a design aid to detect when one wire is connected to too many things.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)

Set Power Connections¶

Uses JSON netlist and module information in Odb to add global power connections for macros at the top level of a design.

If the JSON netlist is hierarchical (e.g. by using a keep hierarchy attribute) this Step emits a warning and does not attempt to connect any macros instantiated within submodules.

Inputs and Outputs¶

Inputs	Outputs
json_h (.h.json)	OpenDB Database (.odb)
odb (.odb)	Design Exchange Format (.def)

Write Verilog Header¶

Writes a Verilog header of the module using information from the generated PDN, guarded by the value of VERILOG_POWER_DEFINE, and the JSON header.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	Verilog Header (.vh)
json_h (.h.json)

Configuration Variables¶

Variable Name	Type	Description	Default
`VERILOG_POWER_DEFINE` Deprecated names `SYNTH_USE_PG_PINS_DEFINES` `SYNTH_POWER_DEFINE`	str?	Specifies the name of the define used to guard power and ground connections in the output Verilog header.	`USE_POWER_PINS`

OpenROAD¶

Clock Tree Synthesis¶

Creates a Clock tree for an ODB file with detailed-placed cells, using reasonably accurate resistance and capacitance estimations. Detailed Placement is then re-performed to accommodate the new cells.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)
	Design Constraints (.sdc)
	Verilog Netlist (.nl.v)
	Powered Verilog Netlist (.pnl.v)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`PL_OPTIMIZE_MIRRORING`	bool	Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design.	`True`
`PL_MAX_DISPLACEMENT_X`	int	Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement.	`500`	µm
`PL_MAX_DISPLACEMENT_Y`	int	Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement.	`100`	µm
`DPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement.	`None`	sites
`CTS_BALANCE_LEVELS`	bool?	Attempts to keep a similar number of levels in the clock tree across non-register cells (e.g., clock-gate or inverter).	`None`
`CTS_SINK_BUFFER_MAX_CAP_DERATE_PCT`	Decimal?	Controls automatic buffer selection. To favor strong(weak) drive strength buffers use a small(large) value.The value of 100 means no derating of max cap limit	`None`
`CTS_DELAY_BUFFER_DERATE_PCT`	Decimal?	This option balances latencies between macro cells and registers by inserting delay buffersThe value of 100 means all needed delay buffers are inserted	`None`
`CTS_OBSTRUCTION_AWARE`	bool?	Enables obstruction-aware buffering such that clock buffers are not placed on top of blockages or hard macros. This option may reduce legalizer displacement, leading to better latency, skew or timing QoR.	`None`
`CTS_SINK_CLUSTERING_ENABLE`	bool	Enables pre-clustering of sinks to create one level of sub-tree before building the H-tree. Each cluster is driven by a buffer which becomes the end point of the H-tree structure.	`True`
`CTS_SINK_CLUSTERING_SIZE`	int?	Specifies the maximum number of sinks per cluster.	`None`
`CTS_SINK_CLUSTERING_MAX_DIAMETER`	Decimal?	Specifies the maximum diameter of the sink cluster.	`None`	µm
`CTS_MACRO_CLUSTERING_SIZE`	int?	Specifies the maximum number of sinks per cluster for the macro tree.	`None`
`CTS_MACRO_CLUSTERING_MAX_DIAMETER`	Decimal?	Specifies the maximum diameter of the sink cluster for the macro tree.	`None`	µm
`CTS_CLK_MAX_WIRE_LENGTH`	Decimal	Specifies the maximum wire length on the clock net.	`0`	µm
`CTS_DISABLE_POST_PROCESSING`	bool	Specifies whether or not to disable post cts processing for outlier sinks.	`False`
`CTS_DISTANCE_BETWEEN_BUFFERS`	Decimal	Specifies the distance between buffers when creating the clock tree.	`0`	µm
`CTS_CORNERS`	List[str]?	Clock tree synthesis step-specific override for PNR_CORNERS.	`None`
`CTS_ROOT_BUFFER` ^PDK	str	Defines the cell inserted at the root of the clock tree. Used in CTS.	`None`
`CTS_CLK_BUFFERS` ^PDK Deprecated names `CTS_CLK_BUFFER_LIST`	List[str]	Defines the list of clock buffer names or buffer name wildcards to be used in CTS.	`None`
`CTS_MAX_CAP`	Decimal?	Overrides the maximum capacitance CTS characterization will test. If omitted, the capacitance is extracted from the lib information of the buffers in CTS_CLK_BUFFERS.	`None`	pF
`CTS_MAX_SLEW`	Decimal?	Overrides the maximum transition time CTS characterization will test. If omitted, the slew is extracted from the lib information of the buffers in CTS_CLK_BUFFERS.	`None`	ns
`CTS_APPLY_NDR`	‘none’｜ ’root_only’｜ ’half’｜ ’full’	Applies 2X spacing non-default rule to clock nets except leaf-level nets following some strategy. There are four strategy options: ‘none’, ‘root_only’, ‘half’, ‘full’.	`half`

Check Antennas¶

Runs OpenROAD to check if one or more long nets may constitute an antenna risk.

The metric route__antenna_violation__count will be updated with the number of violating nets.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)

Configuration Variables¶

Variable Name	Type	Description	Default
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`

Check Macro Instances¶

Checks if all macro instances declared in the configuration are, in fact, in the design, emitting an error otherwise.

Nested macros (macros within macros) are supported provided netlist views are available for the macro.

Inputs and Outputs¶

Inputs	Outputs
nl (.nl.v)

Configuration Variables¶

Variable Name	Type	Description	Default
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`

Check SDC Files¶

Checks that the two variables used for SDC files by OpenROAD steps, namely, PNR_SDC_FILE and SIGNOFF_SDC_FILE, are explicitly set to valid paths by the users, and emits a warning that the fallback will be utilized otherwise.

Configuration Variables¶

Variable Name	Type	Description	Default
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`SIGNOFF_SDC_FILE`	Path?	Specifies the SDC file for STA during signoff	`None`

Cut Rows¶

Cut floorplan rows with respect to placed macros.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`FP_MACRO_HORIZONTAL_HALO` Deprecated names `FP_TAP_HORIZONTAL_HALO`	Decimal	Specify the horizontal halo size around macros.	`10`	µm
`FP_MACRO_VERTICAL_HALO` Deprecated names `FP_TAP_VERTICAL_HALO`	Decimal	Specify the vertical halo size around macros.	`10`	µm
`FP_PRUNE_THRESHOLD` ^PDK	Decimal?	If specified, all rows smaller in width than this value will be removed. This helps avoid “islets” of cells that are hard to route and connect to PDNs.	`None`	µm

DEF to OpenDB¶

Converts a DEF view to an ODB view.

Useful if you have a custom step that manipulates the layout outside of OpenROAD, but you would like to update the OpenROAD database.

Inputs and Outputs¶

Inputs	Outputs
def (.def)	OpenDB Database (.odb)

Configuration Variables¶

Variable Name	Type	Description	Default
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`

Detailed Placement¶

Performs “detailed placement” on an ODB file with global placement. This results in a concrete and legal placement of all cells.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)
	Design Constraints (.sdc)
	Verilog Netlist (.nl.v)
	Powered Verilog Netlist (.pnl.v)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`PL_OPTIMIZE_MIRRORING`	bool	Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design.	`True`
`PL_MAX_DISPLACEMENT_X`	int	Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement.	`500`	µm
`PL_MAX_DISPLACEMENT_Y`	int	Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement.	`100`	µm
`DPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement.	`None`	sites

Detailed Routing¶

The latter phase of routing. This transforms the abstract nets from global routing into wires on the metal layers that respect all design rules, avoids creating accidental shorts, and ensures all wires are connected.

This is by far the longest part of a typical flow, taking hours, days or weeks on larger designs.

After this point, all cells connected to a net can no longer be moved or removed without a custom-written step of some kind that will also rip up wires.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)
	Design Constraints (.sdc)
	Verilog Netlist (.nl.v)
	Powered Verilog Netlist (.pnl.v)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`RT_CLOCK_MIN_LAYER`	str?	The name of lowest layer to be used in routing the clock net.	`None`
`RT_CLOCK_MAX_LAYER`	str?	The name of highest layer to be used in routing the clock net.	`None`
`GRT_ADJUSTMENT`	Decimal	Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction.	`0.3`
`GRT_MACRO_EXTENSION`	int	Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches.	`0`
`GRT_LAYER_ADJUSTMENTS` ^PDK	List[Decimal]	Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1.	`None`
`DIODE_PADDING`	int?	Diode cell padding; increases the width of diode cells during placement checks..	`None`	sites
`GRT_ALLOW_CONGESTION`	bool	Allow congestion during global routing	`False`
`GRT_ANTENNA_REPAIR_ITERS` Deprecated names `GRT_ANT_ITERS` `GRT_ANTENNA_ITERS`	int	The maximum number of iterations for global antenna repairs.	`3`
`GRT_OVERFLOW_ITERS`	int	The maximum number of iterations waiting for the overflow to reach the desired value.	`50`
`GRT_ANTENNA_REPAIR_MARGIN` Deprecated names `GRT_ANT_MARGIN` `GRT_ANTENNA_MARGIN`	int	The margin to over fix antenna violations.	`10`
`GRT_ANTENNA_REPAIR_JUMPER_ONLY`	bool	Only use jumpers to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_DIODE_ONLY.	`False`
`GRT_ANTENNA_REPAIR_DIODE_ONLY`	bool	Only use antenna diodes to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_JUMPER_ONLY.	`False`
`DRT_THREADS` Deprecated names `ROUTING_CORES`	int?	Specifies the number of threads to be used in OpenROAD Detailed Routing. If unset, this will be equal to your machine’s thread count.	`None`
`DRT_OPT_ITERS`	int	Specifies the maximum number of optimization iterations during Detailed Routing in TritonRoute.	`64`
`DRT_SAVE_SNAPSHOTS`	bool	Experimental: saves an odb snapshot of the layout each routing iteration. This increases disk usage considerably but is useful for debugging.	`False`
`DRT_ANTENNA_REPAIR_ITERS`	int	The maximum number of iterations to run antenna repair. Set to a positive integer to attempt to repair antennas and then re-run DRT as appropriate.	`3`
`DRT_ANTENNA_REPAIR_MARGIN` Deprecated names `DRT_ANTENNA_MARGIN`	int	The margin to over fix antenna violations.	`10`
`DRT_ANTENNA_REPAIR_JUMPER_ONLY`	bool	Only use jumpers to fix antenna violations. Cannot be used in conjunction with DRT_ANTENNA_REPAIR_DIODE_ONLY.	`False`
`DRT_ANTENNA_REPAIR_DIODE_ONLY`	bool	Only use antenna diodes to fix antenna violations. Cannot be used in conjunction with DRT_ANTENNA_REPAIR_JUMPER_ONLY.	`False`
`DRT_SAVE_DRC_REPORT_ITERS`	int?	Write a DRC report every N iterations. If DRT_SAVE_SNAPSHOTS is enabled, there is an implicit default value of 1.	`None`
`NON_DEFAULT_RULES`	dict[str, `NDR`]?	Specify non-default rules. Can be used to change the width, spacing and vias of a net.	`None`
`DRT_ASSIGN_NDR`	dict[str, str]?	Specify which nets should be assigned to which non-default rule. The net name is a regular expression. Use ‘^name$’ to match an exact name.	`None`

Dump RC Values¶

Creates three reports:

Initial Database Layer RC Values (from Tech LEF)
Modified Database Layer RC Values
Modified Resizer Layer RC Values

Inputs and Outputs¶

Inputs	Outputs
def (.def)	OpenDB Database (.odb)
	Design Exchange Format (.def)
	Design Constraints (.sdc)
	Verilog Netlist (.nl.v)
	Powered Verilog Netlist (.pnl.v)

Configuration Variables¶

Variable Name	Type	Description	Default
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`

Fill Insertion¶

Fills gaps in the floorplan with filler and decap cells.

This is run after detailed placement. After this point, the design is basically completely hardened.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)
	Design Constraints (.sdc)
	Verilog Netlist (.nl.v)
	Powered Verilog Netlist (.pnl.v)

Configuration Variables¶

Variable Name	Type	Description	Default
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`

Floorplan Initialization¶

Creates DEF and ODB files with the initial floorplan based on the Yosys netlist.

Inputs and Outputs¶

Inputs	Outputs
nl (.nl.v)	OpenDB Database (.odb)
	Design Exchange Format (.def)
	Design Constraints (.sdc)
	Verilog Netlist (.nl.v)
	Powered Verilog Netlist (.pnl.v)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`FP_FLIP_SITES` ^PDK	List[str]?	Flip these sites vertically. Useful in niche alignment scenarios where single-height cells have ground at the south side and double-height cells have power at the south side, causing a short. In that situation, flipping the sites for single-height cells resolves the issue.	`None`
`FP_TRACKS_INFO` ^PDK Deprecated names `TRACKS_INFO_FILE`	Path	A path to the a classic OpenROAD `.tracks` file. Used by the floorplanner to generate tracks.	`None`
`FP_SIZING`	‘absolute’｜ ’relative’	Sizing mode for floorplanning	`relative`
`FP_ASPECT_RATIO`	Decimal	The core’s aspect ratio (height / width).	`1`
`FP_CORE_UTIL`	Decimal	The core utilization percentage.	`50`
`FP_OBSTRUCTIONS`	List[Tuple[Decimal, Decimal, Decimal, Decimal]]?	Obstructions applied at floorplanning stage. Placement sites are never generated at these locations, which guarantees that it will remain empty throughout the entire flow.	`None`	µm
`PL_SOFT_OBSTRUCTIONS`	List[Tuple[Decimal, Decimal, Decimal, Decimal]]?	Soft placement blockages applied at the floorplanning stage. Areas that are soft-blocked will not be used by the initial placer, however, later phases such as buffer insertion or clock tree synthesis are still allowed to place cells in this area.	`None`	µm
`CORE_AREA`	Tuple[Decimal, Decimal, Decimal, Decimal]?	Specifies a core area (i.e. die area minus margins) to be used in floorplanning. It must be paired with `DIE_AREA`.	`None`	µm
`BOTTOM_MARGIN_MULT`	Decimal	The core margin, in multiples of site heights, from the bottom boundary. If `DIEA_AREA` and `CORE_AREA` are set, this variable has no effect.	`4`
`TOP_MARGIN_MULT`	Decimal	The core margin, in multiples of site heights, from the top boundary. If `DIE_AREA` and `CORE_AREA` are set, this variable has no effect.	`4`
`LEFT_MARGIN_MULT`	Decimal	The core margin, in multiples of site widths, from the left boundary. If `DIE_AREA` are `CORE_AREA` are set, this variable has no effect.	`12`
`RIGHT_MARGIN_MULT`	Decimal	The core margin, in multiples of site widths, from the right boundary. If `DIE_AREA` are `CORE_AREA` are set, this variable has no effect.	`12`
`EXTRA_SITES` ^PDK	List[str]?	Explicitly specify sites other than `PLACE_SITE` to create rows for. If the alternate-site standard cells properly declare the `SITE` property, you do not need to provide this explicitly.	`None`

Power Distribution Network Generation¶

Creates a power distribution network on a floorplanned ODB file.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)
	Design Constraints (.sdc)
	Verilog Netlist (.nl.v)
	Powered Verilog Netlist (.pnl.v)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`PDN_SKIPTRIM` Deprecated names `FP_PDN_SKIPTRIM`	bool	Enables `-skip_trim` option during pdngen which skips the metal trim step, which attempts to remove metal stubs.	`False`
`PDN_CORE_RING` Deprecated names `FP_PDN_CORE_RING`	bool	Enables adding a core ring around the design. More details on the control variables in the PDK config documentation.	`False`
`PDN_ENABLE_RAILS` Deprecated names `FP_PDN_ENABLE_RAILS`	bool	Enables the creation of rails in the power grid.	`True`
`PDN_HORIZONTAL_HALO` Deprecated names `FP_PDN_HORIZONTAL_HALO`	Decimal	Sets the horizontal halo around the macros during power grid insertion.	`10`	µm
`PDN_VERTICAL_HALO` Deprecated names `FP_PDN_VERTICAL_HALO`	Decimal	Sets the vertical halo around the macros during power grid insertion.	`10`	µm
`PDN_MULTILAYER` Deprecated names `FP_PDN_MULTILAYER` `DESIGN_IS_CORE`	bool	Controls the layers used in the power grid. If set to false, only the lower layer will be used, which is useful when hardening a macro for integrating into a larger top-level design.	`True`
`PDN_RAIL_OFFSET` ^PDK Deprecated names `FP_PDN_RAIL_OFFSET`	Decimal	The offset for the power distribution network rails for first metal layer.	`None`	µm
`PDN_VWIDTH` ^PDK Deprecated names `FP_PDN_VWIDTH`	Decimal	The strap width for the vertical layer in generated power distribution networks.	`None`	µm
`PDN_HWIDTH` ^PDK Deprecated names `FP_PDN_HWIDTH`	Decimal	The strap width for the horizontal layer in generated power distribution networks.	`None`	µm
`PDN_VSPACING` ^PDK Deprecated names `FP_PDN_VSPACING`	Decimal	Intra-spacing (within a set) of vertical straps in generated power distribution networks.	`None`	µm
`PDN_HSPACING` ^PDK Deprecated names `FP_PDN_HSPACING`	Decimal	Intra-spacing (within a set) of horizontal straps in generated power distribution networks.	`None`	µm
`PDN_VPITCH` ^PDK Deprecated names `FP_PDN_VPITCH`	Decimal	Inter-distance (between sets) of vertical power straps in generated power distribution networks.	`None`	µm
`PDN_HPITCH` ^PDK Deprecated names `FP_PDN_HPITCH`	Decimal	Inter-distance (between sets) of horizontal power straps in generated power distribution networks.	`None`	µm
`PDN_VOFFSET` ^PDK Deprecated names `FP_PDN_VOFFSET`	Decimal	Initial offset for sets of vertical power straps.	`None`	µm
`PDN_HOFFSET` ^PDK Deprecated names `FP_PDN_HOFFSET`	Decimal	Initial offset for sets of horizontal power straps.	`None`	µm
`PDN_CORE_RING_VWIDTH` ^PDK Deprecated names `FP_PDN_CORE_RING_VWIDTH`	Decimal	The width for the vertical layer in the core ring of generated power distribution networks.	`None`	µm
`PDN_CORE_RING_HWIDTH` ^PDK Deprecated names `FP_PDN_CORE_RING_HWIDTH`	Decimal	The width for the horizontal layer in the core ring of generated power distribution networks.	`None`	µm
`PDN_CORE_RING_VSPACING` ^PDK Deprecated names `FP_PDN_CORE_RING_VSPACING`	Decimal	The spacing for the vertical layer in the core ring of generated power distribution networks.	`None`	µm
`PDN_CORE_RING_HSPACING` ^PDK Deprecated names `FP_PDN_CORE_RING_HSPACING`	Decimal	The spacing for the horizontal layer in the core ring of generated power distribution networks.	`None`	µm
`PDN_CORE_RING_VOFFSET` ^PDK Deprecated names `FP_PDN_CORE_RING_VOFFSET`	Decimal	The offset for the vertical layer in the core ring of generated power distribution networks.	`None`	µm
`PDN_CORE_RING_HOFFSET` ^PDK Deprecated names `FP_PDN_CORE_RING_HOFFSET`	Decimal	The offset for the horizontal layer in the core ring of generated power distribution networks.	`None`	µm
`PDN_CORE_RING_CONNECT_TO_PADS` ^PDK	bool	If specified, the core side of the pad pins will be connected to the ring.	`False`
`PDN_CORE_RING_ALLOW_OUT_OF_DIE` ^PDK	bool	If specified, the ring shapes are allowed to be outside the die boundary.	`True`
`PDN_RAIL_LAYER` ^PDK Deprecated names `FP_PDN_RAIL_LAYER` `FP_PDN_RAILS_LAYER`	str	Defines the metal layer used for PDN rails.	`None`
`PDN_RAIL_WIDTH` ^PDK Deprecated names `FP_PDN_RAIL_WIDTH`	Decimal	Defines the width of PDN rails on the `PDN_RAIL_LAYER` layer.	`None`	µm
`PDN_HORIZONTAL_LAYER` ^PDK Deprecated names `FP_PDN_HORIZONTAL_LAYER` `FP_PDN_UPPER_LAYER`	str	Defines the horizontal PDN layer.	`None`
`PDN_VERTICAL_LAYER` ^PDK Deprecated names `FP_PDN_VERTICAL_LAYER` `FP_PDN_LOWER_LAYER`	str	Defines the vertical PDN layer.	`None`
`PDN_CORE_HORIZONTAL_LAYER` ^PDK	str?	Defines the horizontal PDN layer for the core ring. Falls back to `PDN_HORIZONTAL_LAYER` if undefined.	`None`
`PDN_CORE_VERTICAL_LAYER` ^PDK	str?	Defines the vertical PDN layer for the core ring. Falls back to `PDN_VERTICAL_LAYER` if undefined.	`None`
`PDN_EXTEND_TO` ^PDK	‘core_ring’｜ ’boundary’	Defines how far the stripes and rings extend.	`core_ring`
`PDN_ENABLE_PINS` ^PDK	bool	If specified, the power straps will be promoted to block pins.	`True`
`PDN_CFG` Deprecated names `FP_PDN_CFG`	Path?	A custom PDN configuration file. If not provided, the default PDN config will be used.	`None`

Global Placement¶

Performs a somewhat nebulous initial placement for standard cells in a floorplan. While the placement is not concrete, it is enough to start accounting for issues such as fanout, transition time, et cetera.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)
	Design Constraints (.sdc)
	Verilog Netlist (.nl.v)
	Powered Verilog Netlist (.pnl.v)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`RT_CLOCK_MIN_LAYER`	str?	The name of lowest layer to be used in routing the clock net.	`None`
`RT_CLOCK_MAX_LAYER`	str?	The name of highest layer to be used in routing the clock net.	`None`
`GRT_ADJUSTMENT`	Decimal	Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction.	`0.3`
`GRT_MACRO_EXTENSION`	int	Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches.	`0`
`GRT_LAYER_ADJUSTMENTS` ^PDK	List[Decimal]	Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1.	`None`
`PL_OPTIMIZE_MIRRORING`	bool	Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design.	`True`
`PL_MAX_DISPLACEMENT_X`	int	Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement.	`500`	µm
`PL_MAX_DISPLACEMENT_Y`	int	Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement.	`100`	µm
`DPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement.	`None`	sites
`RSZ_DONT_TOUCH_RX` Deprecated names `UNBUFFER_NETS`	str	A single regular expression designating nets or instances as “don’t touch” by design repairs or resizer optimizations.	`$^`
`RSZ_DONT_TOUCH_LIST`	List[str]?	A list of nets and instances as “don’t touch” by design repairs or resizer optimizations.	`None`
`RSZ_CORNERS`	List[str]?	Resizer step-specific override for PNR_CORNERS.	`None`
`PL_TARGET_DENSITY_PCT` Deprecated names `PL_TARGET_DENSITY`	Decimal?	The desired placement density of cells. If not specified, the value will be equal to (`FP_CORE_UTIL` + 5 * `GPL_CELL_PADDING` + 10).	`None`
`PL_SKIP_INITIAL_PLACEMENT`	bool	Specifies whether the placer should run initial placement or not.	`False`
`PL_WIRE_LENGTH_COEF` Deprecated names `PL_WIRELENGTH_COEF`	Decimal	Global placement initial wirelength coefficient. Decreasing the variable will modify the initial placement of the standard cells to reduce the wirelengths	`0.25`
`PL_MIN_PHI_COEFFICIENT`	Decimal?	Sets a lower bound on the µ_k variable in the GPL algorithm. Useful if global placement diverges. See https://openroad.readthedocs.io/en/latest/main/src/gpl/README.html	`None`
`PL_MAX_PHI_COEFFICIENT`	Decimal?	Sets a upper bound on the µ_k variable in the GPL algorithm. Useful if global placement diverges.See https://openroad.readthedocs.io/en/latest/main/src/gpl/README.html	`None`
`FP_CORE_UTIL`	Decimal	The core utilization percentage.	`50`
`GPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for global placement. The number will be integer divided by 2 and placed on both sides.	`None`	sites
`PL_KEEP_RESIZE_BELOW_OVERFLOW`	Decimal?	Only applicable when PL_TIMING_DRIVEN is enabled. When the overflow is below the set value, timing-driven iterations will retain the resizer changes instead of reverting them. Allowed values are 0 to 1. If not set, a nonzero default value from OpenROAD will be used	`None`
`PL_TIMING_DRIVEN` Deprecated names `PL_TIME_DRIVEN`	bool	Specifies whether the placer should use timing-driven placement.	`False`
`PL_ROUTABILITY_DRIVEN`	bool	Specifies whether the placer should use routability driven placement.	`True`
`PL_ROUTABILITY_OVERFLOW_THRESHOLD`	Decimal?	Sets overflow threshold for routability mode.	`None`

Global Placement Skip IO¶

Performs preliminary global placement as a basis for pin placement.

This is useful for flows where the: * Cells are placed * I/Os are placed to match the cells * Cells are then re-placed for an optimal placement

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)
	Design Constraints (.sdc)
	Verilog Netlist (.nl.v)
	Powered Verilog Netlist (.pnl.v)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`RT_CLOCK_MIN_LAYER`	str?	The name of lowest layer to be used in routing the clock net.	`None`
`RT_CLOCK_MAX_LAYER`	str?	The name of highest layer to be used in routing the clock net.	`None`
`GRT_ADJUSTMENT`	Decimal	Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction.	`0.3`
`GRT_MACRO_EXTENSION`	int	Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches.	`0`
`GRT_LAYER_ADJUSTMENTS` ^PDK	List[Decimal]	Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1.	`None`
`PL_OPTIMIZE_MIRRORING`	bool	Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design.	`True`
`PL_MAX_DISPLACEMENT_X`	int	Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement.	`500`	µm
`PL_MAX_DISPLACEMENT_Y`	int	Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement.	`100`	µm
`DPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement.	`None`	sites
`RSZ_DONT_TOUCH_RX` Deprecated names `UNBUFFER_NETS`	str	A single regular expression designating nets or instances as “don’t touch” by design repairs or resizer optimizations.	`$^`
`RSZ_DONT_TOUCH_LIST`	List[str]?	A list of nets and instances as “don’t touch” by design repairs or resizer optimizations.	`None`
`RSZ_CORNERS`	List[str]?	Resizer step-specific override for PNR_CORNERS.	`None`
`PL_TARGET_DENSITY_PCT` Deprecated names `PL_TARGET_DENSITY`	Decimal?	The desired placement density of cells. If not specified, the value will be equal to (`FP_CORE_UTIL` + 5 * `GPL_CELL_PADDING` + 10).	`None`
`PL_SKIP_INITIAL_PLACEMENT`	bool	Specifies whether the placer should run initial placement or not.	`False`
`PL_WIRE_LENGTH_COEF` Deprecated names `PL_WIRELENGTH_COEF`	Decimal	Global placement initial wirelength coefficient. Decreasing the variable will modify the initial placement of the standard cells to reduce the wirelengths	`0.25`
`PL_MIN_PHI_COEFFICIENT`	Decimal?	Sets a lower bound on the µ_k variable in the GPL algorithm. Useful if global placement diverges. See https://openroad.readthedocs.io/en/latest/main/src/gpl/README.html	`None`
`PL_MAX_PHI_COEFFICIENT`	Decimal?	Sets a upper bound on the µ_k variable in the GPL algorithm. Useful if global placement diverges.See https://openroad.readthedocs.io/en/latest/main/src/gpl/README.html	`None`
`FP_CORE_UTIL`	Decimal	The core utilization percentage.	`50`
`GPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for global placement. The number will be integer divided by 2 and placed on both sides.	`None`	sites
`PL_KEEP_RESIZE_BELOW_OVERFLOW`	Decimal?	Only applicable when PL_TIMING_DRIVEN is enabled. When the overflow is below the set value, timing-driven iterations will retain the resizer changes instead of reverting them. Allowed values are 0 to 1. If not set, a nonzero default value from OpenROAD will be used	`None`
`IO_PIN_PLACEMENT_MODE` Deprecated names `FP_PPL_MODE`	‘matching’｜ ’annealing’｜ ’random_equidistant’	Decides the mode of the random IO placement option.	`matching`
`IO_PIN_ORDER_CFG` Deprecated names `FP_PIN_ORDER_CFG`	Path?	Path to a custom pin configuration file.	`None`
`FP_DEF_TEMPLATE`	Path?	Points to the DEF file to be used as a template.	`None`

Global Routing¶

The initial phase of routing. Given a detailed-placed ODB file, this phase starts assigning coarse-grained routing “regions” for each net so they may be later connected to wires.

Estimated capacitance and resistance values are much more accurate for global routing.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`RT_CLOCK_MIN_LAYER`	str?	The name of lowest layer to be used in routing the clock net.	`None`
`RT_CLOCK_MAX_LAYER`	str?	The name of highest layer to be used in routing the clock net.	`None`
`GRT_ADJUSTMENT`	Decimal	Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction.	`0.3`
`GRT_MACRO_EXTENSION`	int	Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches.	`0`
`GRT_LAYER_ADJUSTMENTS` ^PDK	List[Decimal]	Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1.	`None`
`DIODE_PADDING`	int?	Diode cell padding; increases the width of diode cells during placement checks..	`None`	sites
`GRT_ALLOW_CONGESTION`	bool	Allow congestion during global routing	`False`
`GRT_ANTENNA_REPAIR_ITERS` Deprecated names `GRT_ANT_ITERS` `GRT_ANTENNA_ITERS`	int	The maximum number of iterations for global antenna repairs.	`3`
`GRT_OVERFLOW_ITERS`	int	The maximum number of iterations waiting for the overflow to reach the desired value.	`50`
`GRT_ANTENNA_REPAIR_MARGIN` Deprecated names `GRT_ANT_MARGIN` `GRT_ANTENNA_MARGIN`	int	The margin to over fix antenna violations.	`10`
`GRT_ANTENNA_REPAIR_JUMPER_ONLY`	bool	Only use jumpers to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_DIODE_ONLY.	`False`
`GRT_ANTENNA_REPAIR_DIODE_ONLY`	bool	Only use antenna diodes to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_JUMPER_ONLY.	`False`
`PL_OPTIMIZE_MIRRORING`	bool	Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design.	`True`
`PL_MAX_DISPLACEMENT_X`	int	Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement.	`500`	µm
`PL_MAX_DISPLACEMENT_Y`	int	Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement.	`100`	µm
`DPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement.	`None`	sites

I/O Placement¶

Places I/O pins on a floor-planned ODB file using OpenROAD’s built-in placer.

If IO_PIN_ORDER_CFG is not None, this step is skipped (for compatibility with OpenLane.)

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)
	Design Constraints (.sdc)
	Verilog Netlist (.nl.v)
	Powered Verilog Netlist (.pnl.v)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`IO_PIN_H_LAYER` ^PDK Deprecated names `FP_IO_HLAYER`	str	The metal layer on which to place horizontally-aligned (long side parallel with the horizon) pins alongside the east and west edges of the die.	`None`
`IO_PIN_V_LAYER` ^PDK Deprecated names `FP_IO_VLAYER`	str	The metal layer on which to place vertically-aligned (long side perpendicular to the horizon) pins alongside the north and south edges of the die.	`None`
`IO_PIN_V_EXTENSION` Deprecated names `FP_IO_VEXTEND`	Decimal	Extends the vertical io pins outside of the die by the specified units.	`0`	µm
`IO_PIN_H_EXTENSION` Deprecated names `FP_IO_HEXTEND`	Decimal	Extends the horizontal io pins outside of the die by the specified units.	`0`	µm
`IO_PIN_V_THICKNESS_MULT` Deprecated names `FP_IO_VTHICKNESS_MULT`	Decimal	A multiplier for vertical pin thickness. Base thickness is the pins layer min width.	`2`
`IO_PIN_H_THICKNESS_MULT` Deprecated names `FP_IO_HTHICKNESS_MULT`	Decimal	A multiplier for horizontal pin thickness. Base thickness is the pins layer min width.	`2`
`IO_PIN_V_LENGTH` ^PDK Deprecated names `FP_IO_VLENGTH`	Decimal?	The length of the pins with a north or south orientation. If unspecified by a PDK, OpenROAD will use whichever is higher of the following two values: * The pin width * The minimum value satisfying the minimum area constraint given the pin width	`None`	µm
`IO_PIN_H_LENGTH` ^PDK Deprecated names `FP_IO_HLENGTH`	Decimal?	The length of the pins with an east or west orientation. If unspecified by a PDK, OpenROAD will use whichever is higher of the following two values: * The pin width * The minimum value satisfying the minimum area constraint given the pin width	`None`	µm
`IO_PIN_CORNER_AVOIDANCE`	Decimal?	The distance from each corner within which pin placement should be avoided.	`None`	µm
`IO_PIN_PLACEMENT_MODE` Deprecated names `FP_PPL_MODE`	‘matching’｜ ’annealing’｜ ’random_equidistant’	Decides the mode of the random IO placement option.	`matching`
`IO_PIN_MIN_DISTANCE` ^PDK Deprecated names `FP_IO_MIN_DISTANCE`	Decimal?	The minimum distance between two pins. The unit is microns or routing tracks, depending on whether IO_PIN_MIN_DISTANCE_IN_TRACKS is set. If unspecified by a PDK, OpenROAD will use the length of two routing tracks.	`None`	µm or routing tracks
`IO_PIN_MIN_DISTANCE_IN_TRACKS` ^PDK	bool?	Setting this variable to true allows IO_PIN_MIN_DISTANCE to be set in number of tracks instead of microns.	`None`
`IO_PIN_ORDER_CFG` Deprecated names `FP_PIN_ORDER_CFG`	Path?	Path to a custom pin configuration file.	`None`
`IO_EXCLUDE_PIN_REGION`	List[str]?	List of regions where pins cannot be placed. The regions are strings in the format `{edge}:{interval}` where edge is `top\|bottom\|left\|right` and the interval is either `` to exclude the entire edge or `{begin}-{end}` to exclude a part of the edge, where `begin` and `end` are either absolute distance values or themselves `` to denote the very start or end of an edge.	`None`	µm
`FP_DEF_TEMPLATE`	Path?	Points to the DEF file to be used as a template.	`None`

Generate IR Drop Report¶

Performs static IR-drop analysis on the power distribution network. For power nets, this constitutes a decrease in voltage, and for ground nets, it constitutes an increase in voltage.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)
spef (.spef)

Configuration Variables¶

Variable Name	Type	Description	Default
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`VSRC_LOC_FILES`	Dict[str, Path]?	Map of power and ground nets to OpenROAD PSM location files. See this for more info.	`None`

Layout Static Timing Analysis¶

Performs Static Timing Analysis using OpenROAD on the ODB layout in its current state.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)

Configuration Variables¶

Variable Name	Type	Description	Default
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`

Open In GUI¶

Opens the ODB view in the OpenROAD GUI. Useful to inspect some parameters, such as routing density, timing paths, clock tree and whatnot. The LIBs are loaded by default and the SPEFs if available.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)
spef? (.spef)

Configuration Variables¶

Variable Name	Type	Description	Default
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`

Pad Ring Generation¶

Assembles a pad ring on a floor-planned ODB file using OpenROAD’s built-in pad placer.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)
	Design Constraints (.sdc)
	Verilog Netlist (.nl.v)
	Powered Verilog Netlist (.pnl.v)

Configuration Variables¶

Variable Name	Type	Description	Default
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PAD_CFG`	Path?	A custom pad configuration file. If not provided, the default pad config will be used.	`None`
`PAD_SOUTH`	List[str]?	The pad instance names for the south pad row.	`None`
`PAD_EAST`	List[str]?	The pad instance names for the east pad row.	`None`
`PAD_NORTH`	List[str]?	The pad instance names for the north pad row.	`None`
`PAD_WEST`	List[str]?	The pad instance names for the west pad row.	`None`

Parasitic Resistance/Capacitance Extraction¶

This extracts parasitic electrical values from a detailed-placed circuit. These can be used to create basically the highest accurate STA possible for a given design.

Inputs and Outputs¶

Inputs	Outputs
def (.def)	Standard Parasitics Extraction Format (.spef)

Configuration Variables¶

Variable Name	Type	Description	Default
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`RCX_MERGE_VIA_WIRE_RES`	bool	If enabled, the via and wire resistances will be merged.	`True`
`RCX_SDC_FILE`	Path?	Specifies SDC file to be used for RCX-based STA, which can be different from the one used for implementation.	`None`
`RCX_RULESETS` ^PDK	Dict[str, Path]	Map of corner patterns to OpenRCX extraction rules.	`None`
`STA_THREADS`	int?	The maximum number of STA corners to run in parallel. If unset, this will be equal to your machine’s thread count.	`None`

Antenna Repair¶

Applies antenna effect mitigations using global-routing information, then re-runs detailed placement and global routing to legalize any inserted diodes.

An antenna check is once again performed, updating the route__antenna_violation__count metric.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	Design Exchange Format (.def)
	OpenDB Database (.odb)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`RT_CLOCK_MIN_LAYER`	str?	The name of lowest layer to be used in routing the clock net.	`None`
`RT_CLOCK_MAX_LAYER`	str?	The name of highest layer to be used in routing the clock net.	`None`
`GRT_ADJUSTMENT`	Decimal	Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction.	`0.3`
`GRT_MACRO_EXTENSION`	int	Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches.	`0`
`GRT_LAYER_ADJUSTMENTS` ^PDK	List[Decimal]	Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1.	`None`
`DIODE_PADDING`	int?	Diode cell padding; increases the width of diode cells during placement checks..	`None`	sites
`GRT_ALLOW_CONGESTION`	bool	Allow congestion during global routing	`False`
`GRT_ANTENNA_REPAIR_ITERS` Deprecated names `GRT_ANT_ITERS` `GRT_ANTENNA_ITERS`	int	The maximum number of iterations for global antenna repairs.	`3`
`GRT_OVERFLOW_ITERS`	int	The maximum number of iterations waiting for the overflow to reach the desired value.	`50`
`GRT_ANTENNA_REPAIR_MARGIN` Deprecated names `GRT_ANT_MARGIN` `GRT_ANTENNA_MARGIN`	int	The margin to over fix antenna violations.	`10`
`GRT_ANTENNA_REPAIR_JUMPER_ONLY`	bool	Only use jumpers to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_DIODE_ONLY.	`False`
`GRT_ANTENNA_REPAIR_DIODE_ONLY`	bool	Only use antenna diodes to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_JUMPER_ONLY.	`False`
`PL_OPTIMIZE_MIRRORING`	bool	Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design.	`True`
`PL_MAX_DISPLACEMENT_X`	int	Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement.	`500`	µm
`PL_MAX_DISPLACEMENT_Y`	int	Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement.	`100`	µm
`DPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement.	`None`	sites

Repair Design (Post-Global Placement)¶

This is identical to OpenROAD.RepairDesignPostGPL. It is retained for backwards compatibility.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)
	Design Constraints (.sdc)
	Verilog Netlist (.nl.v)
	Powered Verilog Netlist (.pnl.v)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`RT_CLOCK_MIN_LAYER`	str?	The name of lowest layer to be used in routing the clock net.	`None`
`RT_CLOCK_MAX_LAYER`	str?	The name of highest layer to be used in routing the clock net.	`None`
`GRT_ADJUSTMENT`	Decimal	Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction.	`0.3`
`GRT_MACRO_EXTENSION`	int	Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches.	`0`
`GRT_LAYER_ADJUSTMENTS` ^PDK	List[Decimal]	Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1.	`None`
`DIODE_PADDING`	int?	Diode cell padding; increases the width of diode cells during placement checks..	`None`	sites
`GRT_ALLOW_CONGESTION`	bool	Allow congestion during global routing	`False`
`GRT_ANTENNA_REPAIR_ITERS` Deprecated names `GRT_ANT_ITERS` `GRT_ANTENNA_ITERS`	int	The maximum number of iterations for global antenna repairs.	`3`
`GRT_OVERFLOW_ITERS`	int	The maximum number of iterations waiting for the overflow to reach the desired value.	`50`
`GRT_ANTENNA_REPAIR_MARGIN` Deprecated names `GRT_ANT_MARGIN` `GRT_ANTENNA_MARGIN`	int	The margin to over fix antenna violations.	`10`
`GRT_ANTENNA_REPAIR_JUMPER_ONLY`	bool	Only use jumpers to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_DIODE_ONLY.	`False`
`GRT_ANTENNA_REPAIR_DIODE_ONLY`	bool	Only use antenna diodes to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_JUMPER_ONLY.	`False`
`PL_OPTIMIZE_MIRRORING`	bool	Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design.	`True`
`PL_MAX_DISPLACEMENT_X`	int	Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement.	`500`	µm
`PL_MAX_DISPLACEMENT_Y`	int	Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement.	`100`	µm
`DPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement.	`None`	sites
`RSZ_DONT_TOUCH_RX` Deprecated names `UNBUFFER_NETS`	str	A single regular expression designating nets or instances as “don’t touch” by design repairs or resizer optimizations.	`$^`
`RSZ_DONT_TOUCH_LIST`	List[str]?	A list of nets and instances as “don’t touch” by design repairs or resizer optimizations.	`None`
`RSZ_CORNERS`	List[str]?	Resizer step-specific override for PNR_CORNERS.	`None`
`DESIGN_REPAIR_BUFFER_INPUT_PORTS` Deprecated names `PL_RESIZER_BUFFER_INPUT_PORTS`	bool	Specifies whether or not to insert buffers on input ports when design repairs are run.	`True`
`DESIGN_REPAIR_BUFFER_OUTPUT_PORTS` Deprecated names `PL_RESIZER_BUFFER_OUTPUT_PORTS`	bool	Specifies whether or not to insert buffers on output ports when design repairs are run.	`True`
`DESIGN_REPAIR_TIE_FANOUT` Deprecated names `PL_RESIZER_REPAIR_TIE_FANOUT`	bool	Specifies whether or not to repair tie cells fanout when design repairs are run.	`True`
`DESIGN_REPAIR_TIE_SEPARATION` Deprecated names `PL_RESIZER_TIE_SEPERATION`	bool	Allows tie separation when performing design repairs.	`False`
`DESIGN_REPAIR_MAX_WIRE_LENGTH` Deprecated names `PL_RESIZER_MAX_WIRE_LENGTH`	Decimal	Specifies the maximum wire length cap used by resizer to insert buffers during design repair. If set to 0, no buffers will be inserted.	`0`	µm
`DESIGN_REPAIR_MAX_SLEW_PCT` Deprecated names `PL_RESIZER_MAX_SLEW_MARGIN`	Decimal	Specifies a margin for the slews during design repair.	`20`
`DESIGN_REPAIR_MAX_CAP_PCT` Deprecated names `PL_RESIZER_MAX_CAP_MARGIN`	Decimal	Specifies a margin for the capacitances during design repair.	`20`
`DESIGN_REPAIR_REMOVE_BUFFERS`	bool	Invokes OpenROAD’s remove_buffers command to remove buffers from synthesis, which gives OpenROAD more flexibility when buffering nets.	`False`

Repair Design (Post-Global Placement)¶

Runs a number of design “repairs” on a global-placed ODB file.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)
	Design Constraints (.sdc)
	Verilog Netlist (.nl.v)
	Powered Verilog Netlist (.pnl.v)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`RT_CLOCK_MIN_LAYER`	str?	The name of lowest layer to be used in routing the clock net.	`None`
`RT_CLOCK_MAX_LAYER`	str?	The name of highest layer to be used in routing the clock net.	`None`
`GRT_ADJUSTMENT`	Decimal	Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction.	`0.3`
`GRT_MACRO_EXTENSION`	int	Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches.	`0`
`GRT_LAYER_ADJUSTMENTS` ^PDK	List[Decimal]	Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1.	`None`
`DIODE_PADDING`	int?	Diode cell padding; increases the width of diode cells during placement checks..	`None`	sites
`GRT_ALLOW_CONGESTION`	bool	Allow congestion during global routing	`False`
`GRT_ANTENNA_REPAIR_ITERS` Deprecated names `GRT_ANT_ITERS` `GRT_ANTENNA_ITERS`	int	The maximum number of iterations for global antenna repairs.	`3`
`GRT_OVERFLOW_ITERS`	int	The maximum number of iterations waiting for the overflow to reach the desired value.	`50`
`GRT_ANTENNA_REPAIR_MARGIN` Deprecated names `GRT_ANT_MARGIN` `GRT_ANTENNA_MARGIN`	int	The margin to over fix antenna violations.	`10`
`GRT_ANTENNA_REPAIR_JUMPER_ONLY`	bool	Only use jumpers to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_DIODE_ONLY.	`False`
`GRT_ANTENNA_REPAIR_DIODE_ONLY`	bool	Only use antenna diodes to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_JUMPER_ONLY.	`False`
`PL_OPTIMIZE_MIRRORING`	bool	Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design.	`True`
`PL_MAX_DISPLACEMENT_X`	int	Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement.	`500`	µm
`PL_MAX_DISPLACEMENT_Y`	int	Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement.	`100`	µm
`DPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement.	`None`	sites
`RSZ_DONT_TOUCH_RX` Deprecated names `UNBUFFER_NETS`	str	A single regular expression designating nets or instances as “don’t touch” by design repairs or resizer optimizations.	`$^`
`RSZ_DONT_TOUCH_LIST`	List[str]?	A list of nets and instances as “don’t touch” by design repairs or resizer optimizations.	`None`
`RSZ_CORNERS`	List[str]?	Resizer step-specific override for PNR_CORNERS.	`None`
`DESIGN_REPAIR_BUFFER_INPUT_PORTS` Deprecated names `PL_RESIZER_BUFFER_INPUT_PORTS`	bool	Specifies whether or not to insert buffers on input ports when design repairs are run.	`True`
`DESIGN_REPAIR_BUFFER_OUTPUT_PORTS` Deprecated names `PL_RESIZER_BUFFER_OUTPUT_PORTS`	bool	Specifies whether or not to insert buffers on output ports when design repairs are run.	`True`
`DESIGN_REPAIR_TIE_FANOUT` Deprecated names `PL_RESIZER_REPAIR_TIE_FANOUT`	bool	Specifies whether or not to repair tie cells fanout when design repairs are run.	`True`
`DESIGN_REPAIR_TIE_SEPARATION` Deprecated names `PL_RESIZER_TIE_SEPERATION`	bool	Allows tie separation when performing design repairs.	`False`
`DESIGN_REPAIR_MAX_WIRE_LENGTH` Deprecated names `PL_RESIZER_MAX_WIRE_LENGTH`	Decimal	Specifies the maximum wire length cap used by resizer to insert buffers during design repair. If set to 0, no buffers will be inserted.	`0`	µm
`DESIGN_REPAIR_MAX_SLEW_PCT` Deprecated names `PL_RESIZER_MAX_SLEW_MARGIN`	Decimal	Specifies a margin for the slews during design repair.	`20`
`DESIGN_REPAIR_MAX_CAP_PCT` Deprecated names `PL_RESIZER_MAX_CAP_MARGIN`	Decimal	Specifies a margin for the capacitances during design repair.	`20`
`DESIGN_REPAIR_REMOVE_BUFFERS`	bool	Invokes OpenROAD’s remove_buffers command to remove buffers from synthesis, which gives OpenROAD more flexibility when buffering nets.	`False`

Repair Design (Post-Global Routing)¶

Runs a number of design “repairs” on a global-routed ODB file.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)
	Design Constraints (.sdc)
	Verilog Netlist (.nl.v)
	Powered Verilog Netlist (.pnl.v)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`RT_CLOCK_MIN_LAYER`	str?	The name of lowest layer to be used in routing the clock net.	`None`
`RT_CLOCK_MAX_LAYER`	str?	The name of highest layer to be used in routing the clock net.	`None`
`GRT_ADJUSTMENT`	Decimal	Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction.	`0.3`
`GRT_MACRO_EXTENSION`	int	Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches.	`0`
`GRT_LAYER_ADJUSTMENTS` ^PDK	List[Decimal]	Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1.	`None`
`DIODE_PADDING`	int?	Diode cell padding; increases the width of diode cells during placement checks..	`None`	sites
`GRT_ALLOW_CONGESTION`	bool	Allow congestion during global routing	`False`
`GRT_ANTENNA_REPAIR_ITERS` Deprecated names `GRT_ANT_ITERS` `GRT_ANTENNA_ITERS`	int	The maximum number of iterations for global antenna repairs.	`3`
`GRT_OVERFLOW_ITERS`	int	The maximum number of iterations waiting for the overflow to reach the desired value.	`50`
`GRT_ANTENNA_REPAIR_MARGIN` Deprecated names `GRT_ANT_MARGIN` `GRT_ANTENNA_MARGIN`	int	The margin to over fix antenna violations.	`10`
`GRT_ANTENNA_REPAIR_JUMPER_ONLY`	bool	Only use jumpers to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_DIODE_ONLY.	`False`
`GRT_ANTENNA_REPAIR_DIODE_ONLY`	bool	Only use antenna diodes to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_JUMPER_ONLY.	`False`
`PL_OPTIMIZE_MIRRORING`	bool	Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design.	`True`
`PL_MAX_DISPLACEMENT_X`	int	Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement.	`500`	µm
`PL_MAX_DISPLACEMENT_Y`	int	Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement.	`100`	µm
`DPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement.	`None`	sites
`RSZ_DONT_TOUCH_RX` Deprecated names `UNBUFFER_NETS`	str	A single regular expression designating nets or instances as “don’t touch” by design repairs or resizer optimizations.	`$^`
`RSZ_DONT_TOUCH_LIST`	List[str]?	A list of nets and instances as “don’t touch” by design repairs or resizer optimizations.	`None`
`RSZ_CORNERS`	List[str]?	Resizer step-specific override for PNR_CORNERS.	`None`
`GRT_DESIGN_REPAIR_RUN_GRT`	bool	Enables running GRT before and after running resizer	`True`
`GRT_DESIGN_REPAIR_MAX_WIRE_LENGTH` Deprecated names `GLB_RESIZER_MAX_WIRE_LENGTH`	Decimal	Specifies the maximum wire length cap used by resizer to insert buffers during post-grt design repair. If set to 0, no buffers will be inserted.	`0`	µm
`GRT_DESIGN_REPAIR_MAX_SLEW_PCT` Deprecated names `GLB_RESIZER_MAX_SLEW_MARGIN`	Decimal	Specifies a margin for the slews during post-grt design repair.	`10`
`GRT_DESIGN_REPAIR_MAX_CAP_PCT` Deprecated names `GLB_RESIZER_MAX_CAP_MARGIN`	Decimal	Specifies a margin for the capacitances during design post-grt repair.	`10`

Resizer Timing Optimizations (Post-Clock Tree Synthesis)¶

First attempt to meet timing requirements for a cell based on basic timing information after clock tree synthesis.

Standard cells may be resized, and buffer cells may be inserted to ensure that no hold violations exist and no setup violations exist at the current clock.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)
	Design Constraints (.sdc)
	Verilog Netlist (.nl.v)
	Powered Verilog Netlist (.pnl.v)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`RT_CLOCK_MIN_LAYER`	str?	The name of lowest layer to be used in routing the clock net.	`None`
`RT_CLOCK_MAX_LAYER`	str?	The name of highest layer to be used in routing the clock net.	`None`
`GRT_ADJUSTMENT`	Decimal	Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction.	`0.3`
`GRT_MACRO_EXTENSION`	int	Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches.	`0`
`GRT_LAYER_ADJUSTMENTS` ^PDK	List[Decimal]	Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1.	`None`
`DIODE_PADDING`	int?	Diode cell padding; increases the width of diode cells during placement checks..	`None`	sites
`GRT_ALLOW_CONGESTION`	bool	Allow congestion during global routing	`False`
`GRT_ANTENNA_REPAIR_ITERS` Deprecated names `GRT_ANT_ITERS` `GRT_ANTENNA_ITERS`	int	The maximum number of iterations for global antenna repairs.	`3`
`GRT_OVERFLOW_ITERS`	int	The maximum number of iterations waiting for the overflow to reach the desired value.	`50`
`GRT_ANTENNA_REPAIR_MARGIN` Deprecated names `GRT_ANT_MARGIN` `GRT_ANTENNA_MARGIN`	int	The margin to over fix antenna violations.	`10`
`GRT_ANTENNA_REPAIR_JUMPER_ONLY`	bool	Only use jumpers to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_DIODE_ONLY.	`False`
`GRT_ANTENNA_REPAIR_DIODE_ONLY`	bool	Only use antenna diodes to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_JUMPER_ONLY.	`False`
`PL_OPTIMIZE_MIRRORING`	bool	Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design.	`True`
`PL_MAX_DISPLACEMENT_X`	int	Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement.	`500`	µm
`PL_MAX_DISPLACEMENT_Y`	int	Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement.	`100`	µm
`DPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement.	`None`	sites
`RSZ_DONT_TOUCH_RX` Deprecated names `UNBUFFER_NETS`	str	A single regular expression designating nets or instances as “don’t touch” by design repairs or resizer optimizations.	`$^`
`RSZ_DONT_TOUCH_LIST`	List[str]?	A list of nets and instances as “don’t touch” by design repairs or resizer optimizations.	`None`
`RSZ_CORNERS`	List[str]?	Resizer step-specific override for PNR_CORNERS.	`None`
`PL_RESIZER_HOLD_SLACK_MARGIN`	Decimal	Specifies a time margin for the slack when fixing hold violations. Normally the resizer will stop when it reaches zero slack. This option allows you to overfix.	`0.1`	ns
`PL_RESIZER_SETUP_SLACK_MARGIN`	Decimal	Specifies a time margin for the slack when fixing setup violations.	`0.05`	ns
`PL_RESIZER_HOLD_MAX_BUFFER_PCT` Deprecated names `PL_RESIZER_HOLD_MAX_BUFFER_PERCENT`	Decimal	Specifies a max number of buffers to insert to fix hold violations. This number is calculated as a percentage of the number of instances in the design.	`50`
`PL_RESIZER_SETUP_MAX_BUFFER_PCT` Deprecated names `PL_RESIZER_SETUP_MAX_BUFFER_PERCENT`	Decimal	Specifies a max number of buffers to insert to fix setup violations. This number is calculated as a percentage of the number of instances in the design.	`50`
`PL_RESIZER_ALLOW_SETUP_VIOS`	bool	Allows the creation of setup violations when fixing hold violations. Setup violations are less dangerous as they simply mean a chip may not run at its rated speed, however, chips with hold violations are essentially dead-on-arrival.	`False`
`PL_RESIZER_SETUP_GATE_CLONING` Deprecated names `PL_RESIZER_GATE_CLONING`	bool	Enables gate cloning when attempting to fix setup violations	`True`
`PL_RESIZER_SETUP_BUFFERING`	bool	Rebuffering and load splitting during setup fixing.	`True`
`PL_RESIZER_SETUP_BUFFER_REMOVAL`	bool	Buffer removal transform during setup fixing.	`True`
`PL_RESIZER_SETUP_REPAIR_TNS_PCT`	Decimal?	Percentage of violating endpoints to repair during setup fixing.	`None`
`PL_RESIZER_SETUP_MAX_UTIL_PCT`	Decimal?	Defines the percentage of core area used during setup fixing.	`None`
`PL_RESIZER_HOLD_REPAIR_TNS_PCT`	Decimal?	Percentage of violating endpoints to repair during hold fixing.	`None`
`PL_RESIZER_HOLD_MAX_UTIL_PCT`	Decimal?	Defines the percentage of core area used during hold fixing.	`None`
`PL_RESIZER_FIX_HOLD_FIRST`	bool	Experimental: attempt to fix hold violations before setup violations, which may lead to better timing results.	`False`

Resizer Timing Optimizations (Post-Global Routing)¶

Second attempt to meet timing requirements for a cell based on timing information after estimating resistance and capacitance values based on global routing.

Standard cells may be resized, and buffer cells may be inserted to ensure that no hold violations exist and no setup violations exist at the current clock.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)
	Design Constraints (.sdc)
	Verilog Netlist (.nl.v)
	Powered Verilog Netlist (.pnl.v)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`RT_CLOCK_MIN_LAYER`	str?	The name of lowest layer to be used in routing the clock net.	`None`
`RT_CLOCK_MAX_LAYER`	str?	The name of highest layer to be used in routing the clock net.	`None`
`GRT_ADJUSTMENT`	Decimal	Reduction in the routing capacity of the edges between the cells in the global routing graph for all layers. Values range from 0 to 1. 1 = most reduction, 0 = least reduction.	`0.3`
`GRT_MACRO_EXTENSION`	int	Sets the number of GCells added to the blockages boundaries from macros. A GCell is typically defined in terms of Mx routing tracks. The default GCell size is 15 M3 pitches.	`0`
`GRT_LAYER_ADJUSTMENTS` ^PDK	List[Decimal]	Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 through 1.	`None`
`DIODE_PADDING`	int?	Diode cell padding; increases the width of diode cells during placement checks..	`None`	sites
`GRT_ALLOW_CONGESTION`	bool	Allow congestion during global routing	`False`
`GRT_ANTENNA_REPAIR_ITERS` Deprecated names `GRT_ANT_ITERS` `GRT_ANTENNA_ITERS`	int	The maximum number of iterations for global antenna repairs.	`3`
`GRT_OVERFLOW_ITERS`	int	The maximum number of iterations waiting for the overflow to reach the desired value.	`50`
`GRT_ANTENNA_REPAIR_MARGIN` Deprecated names `GRT_ANT_MARGIN` `GRT_ANTENNA_MARGIN`	int	The margin to over fix antenna violations.	`10`
`GRT_ANTENNA_REPAIR_JUMPER_ONLY`	bool	Only use jumpers to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_DIODE_ONLY.	`False`
`GRT_ANTENNA_REPAIR_DIODE_ONLY`	bool	Only use antenna diodes to fix antenna violations. Cannot be used in conjunction with GRT_ANTENNA_REPAIR_JUMPER_ONLY.	`False`
`PL_OPTIMIZE_MIRRORING`	bool	Specifies whether or not to run an optimize_mirroring pass whenever detailed placement happens. This pass will mirror the cells whenever possible to optimize the design.	`True`
`PL_MAX_DISPLACEMENT_X`	int	Specifies how far an instance can be moved along the X-axis when finding a site where it can be placed during detailed placement.	`500`	µm
`PL_MAX_DISPLACEMENT_Y`	int	Specifies how far an instance can be moved along the Y-axis when finding a site where it can be placed during detailed placement.	`100`	µm
`DPL_CELL_PADDING` ^PDK	int	Cell padding value (in sites) for detailed placement. The number will be integer divided by 2 and placed on both sides. Should be <= global placement.	`None`	sites
`RSZ_DONT_TOUCH_RX` Deprecated names `UNBUFFER_NETS`	str	A single regular expression designating nets or instances as “don’t touch” by design repairs or resizer optimizations.	`$^`
`RSZ_DONT_TOUCH_LIST`	List[str]?	A list of nets and instances as “don’t touch” by design repairs or resizer optimizations.	`None`
`RSZ_CORNERS`	List[str]?	Resizer step-specific override for PNR_CORNERS.	`None`
`GRT_RESIZER_HOLD_SLACK_MARGIN` Deprecated names `GLB_RESIZER_HOLD_SLACK_MARGIN`	Decimal	Specifies a time margin for the slack when fixing hold violations. Normally the resizer will stop when it reaches zero slack. This option allows you to overfix.	`0.05`	ns
`GRT_RESIZER_SETUP_SLACK_MARGIN` Deprecated names `GLB_RESIZER_SETUP_SLACK_MARGIN`	Decimal	Specifies a time margin for the slack when fixing setup violations.	`0.025`	ns
`GRT_RESIZER_HOLD_MAX_BUFFER_PCT` Deprecated names `GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT`	Decimal	Specifies a max number of buffers to insert to fix hold violations. This number is calculated as a percentage of the number of instances in the design.	`50`
`GRT_RESIZER_SETUP_MAX_BUFFER_PCT` Deprecated names `GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT`	Decimal	Specifies a max number of buffers to insert to fix setup violations. This number is calculated as a percentage of the number of instances in the design.	`50`
`GRT_RESIZER_ALLOW_SETUP_VIOS` Deprecated names `GLB_RESIZER_ALLOW_SETUP_VIOS`	bool	Allows setup violations when fixing hold.	`False`
`GRT_RESIZER_SETUP_GATE_CLONING` Deprecated names `GRT_RESIZER_GATE_CLONING`	bool	Enables gate cloning when attempting to fix setup violations	`True`
`GRT_RESIZER_RUN_GRT`	bool	Gates running global routing after resizer steps. May be useful to disable for designs where global routing takes non-trivial time.	`True`
`GRT_RESIZER_SETUP_BUFFERING`	bool	Rebuffering and load splitting during setup fixing.	`True`
`GRT_RESIZER_SETUP_BUFFER_REMOVAL`	bool	Buffer removal transform during setup fixing.	`True`
`GRT_RESIZER_SETUP_REPAIR_TNS_PCT`	Decimal?	Percentage of violating endpoints to repair during setup fixing.	`None`
`GRT_RESIZER_SETUP_MAX_UTIL_PCT`	Decimal?	Defines the percentage of core area used during setup fixing.	`None`
`GRT_RESIZER_HOLD_REPAIR_TNS_PCT`	Decimal?	Percentage of violating endpoints to repair during hold fixing.	`None`
`GRT_RESIZER_HOLD_MAX_UTIL_PCT`	Decimal?	Defines the percentage of core area used during hold fixing.	`None`
`GRT_RESIZER_FIX_HOLD_FIRST`	bool	Experimental: attempt to fix hold violations before setup violations, which may lead to better timing results.	`False`

Static Timing Analysis (Mid-PnR)¶

Performs Static Timing Analysis using OpenROAD on an OpenROAD database, mid-PnR, with estimated values for parasitics.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)

Configuration Variables¶

Variable Name	Type	Description	Default
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`

Static Timing Analysis (Post-PnR)¶

Performs multi-corner Static Timing Analysis using OpenSTA on the post-PnR Verilog netlist, with extracted parasitics for both the top-level module and any associated macros.

During this step, the special variable OPENLANE_SDC_IDEAL_CLOCKS is exposed to SDC files with a value of 0. We encourage PNR SDC files to use propagated clocks at this stage based on this variable’s existence and value.

Inputs and Outputs¶

Inputs	Outputs
nl (.nl.v)	Standard Delay Format (.sdf)
spef (.spef)	Design Constraints (.sdc)
odb? (.odb)	LIB Timing Library Format (.lib)

Configuration Variables¶

Variable Name	Type	Description	Default
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`STA_MACRO_PRIORITIZE_NL`	bool	Prioritize the use of Netlists + SPEF files over LIB files if available for Macros. Useful if extraction was done using OpenROAD, where SPEF files are far more accurate.	`True`
`STA_MAX_VIOLATOR_COUNT`	int?	Maximum number of violators to list in violator_list.rpt	`None`
`EXTRA_SPEFS`	List[(str｜Path)]?	A variable that only exists for backwards compatibility with LibreLane <2.0.0 and should not be used by new designs.	`None`
`STA_THREADS`	int?	The maximum number of STA corners to run in parallel. If unset, this will be equal to your machine’s thread count.	`None`
`SIGNOFF_SDC_FILE`	Path?	Specifies the SDC file for STA during signoff	`None`

Static Timing Analysis (Pre-PnR)¶

Performs hierarchical Static Timing Analysis using OpenSTA on the pre-PnR Verilog netlist, with all available timing information for standard cells and macros for multiple corners.

If timing information is not available for a Macro, the macro in question will be black-boxed.

During this step, the special variable OPENLANE_SDC_IDEAL_CLOCKS is exposed to SDC files with a value of 1. We encourage PNR SDC files to use ideal clocks at this stage based on this variable’s existence and value.

Inputs and Outputs¶

Inputs	Outputs
nl (.nl.v)	Standard Delay Format (.sdf)
	Design Constraints (.sdc)

Configuration Variables¶

Variable Name	Type	Description	Default
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`STA_MACRO_PRIORITIZE_NL`	bool	Prioritize the use of Netlists + SPEF files over LIB files if available for Macros. Useful if extraction was done using OpenROAD, where SPEF files are far more accurate.	`True`
`STA_MAX_VIOLATOR_COUNT`	int?	Maximum number of violators to list in violator_list.rpt	`None`
`EXTRA_SPEFS`	List[(str｜Path)]?	A variable that only exists for backwards compatibility with LibreLane <2.0.0 and should not be used by new designs.	`None`
`STA_THREADS`	int?	The maximum number of STA corners to run in parallel. If unset, this will be equal to your machine’s thread count.	`None`

Tap/Decap Insertion¶

Places welltap cells across a floorplan, as well as endcap cells at the edges of the floorplan.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)
	Design Constraints (.sdc)
	Verilog Netlist (.nl.v)
	Powered Verilog Netlist (.pnl.v)

Configuration Variables¶

Variable Name	Type	Description	Default	Units
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`
`FP_TAPCELL_DIST` ^PDK	Decimal?	The distance between tap cell columns. Must be specified if WELLTAP_CELL is specified.	`None`	µm
`FP_MACRO_HORIZONTAL_HALO` Deprecated names `FP_TAP_HORIZONTAL_HALO`	Decimal	Specify the horizontal halo size around macros.	`10`	µm
`FP_MACRO_VERTICAL_HALO` Deprecated names `FP_TAP_VERTICAL_HALO`	Decimal	Specify the vertical halo size around macros.	`10`	µm

Unplace All¶

Sets placement status of all instances to NONE.

Useful in flows where a preliminary placement is needed as a pre-requisite to something else but that placement must be discarded.

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	OpenDB Database (.odb)
	Design Exchange Format (.def)
	Design Constraints (.sdc)
	Verilog Netlist (.nl.v)
	Powered Verilog Netlist (.pnl.v)

Configuration Variables¶

Variable Name	Type	Description	Default
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`

Write CDL¶

Write CDL view of an ODB design

Inputs and Outputs¶

Inputs	Outputs
odb (.odb)	Circuit Design Language (.cdl)

Configuration Variables¶

Variable Name	Type	Description	Default
`PNR_CORNERS` ^PDK	List[str]?	A list of fully-qualified IPVT corners to use during PnR. If unspecified, the value for `STA_CORNERS` from the PDK will be used.	`None`
`SET_RC_VERBOSE`	bool	If set to true, set_rc commands are echoed. Quite noisy, but may be useful for debugging.	`False`
`LAYERS_RC` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance and capacitance values for metal layers. For each IPVT corner, a mapping for each metal layer is provided. Each mapping describes custom resistance and capacitance values. Usage of wildcards for specifying IPVT corners is allowed. Units are resistance and capacitance per unit length as defined in the first lib file.	`None`
`VIAS_R` ^PDK	Dict[str, Dict[str, Dict[str, Decimal]]]?	Used during PNR steps, Specific custom resistance values for via layers. For each IPVT corner, a mapping for each via layer is provided. Each mapping describes custom resistance values. Usage of wildcards for specifying IPVT corners is allowed. Via resistance is per cut/via with units asdefined in the first lib file.	`None`
`SIGNAL_WIRE_RC_LAYERS` ^PDK Deprecated names `WIRE_RC_LAYER` `DATA_WIRE_RC_LAYER`	List[str]?	Sets estimated signal wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`CLOCK_WIRE_RC_LAYERS` ^PDK Deprecated names `CLOCK_WIRE_RC_LAYER`	List[str]?	Sets estimated clock wire RC values to the average of these layers’. If you provide more than two, the averages are grouped by preferred routing direction and you must provide at least one layer for each routing direction.	`None`
`PDN_CONNECT_MACROS_TO_GRID` Deprecated names `FP_PDN_ENABLE_MACROS_GRID`	bool	Enables the connection of macros to the top level power grid.	`True`
`PDN_MACRO_CONNECTIONS` Deprecated names `FP_PDN_MACRO_HOOKS`	List[str]?	Specifies explicit power connections of internal macros to the top level power grid, in the format: regex matching macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names `<instance_name_rx> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>`.	`None`
`PDN_ENABLE_GLOBAL_CONNECTIONS` Deprecated names `FP_PDN_ENABLE_GLOBAL_CONNECTIONS`	bool	Enables the creation of global connections in PDN generation.	`True`
`PNR_SDC_FILE`	Path?	Specifies the SDC file used during all implementation (PnR) steps	`None`
`STA_EXTRA_CORNER_TCL_FILE`	Path?	Experimental: specifies a additional configuration .tcl file to be called during (PnR) steps.	`None`
`DEDUPLICATE_CORNERS`	bool	Cull duplicate IPVT corners during PNR, i.e. corners that share the same set of lib files and values for LAYERS_RC and VIAS_R as another corner are not considered outside of STA.	`False`

Verilator¶

Verilator Lint¶

Lints inputs RTL Verilog files.

The linting is done with the defines for power and ground inputs on, as more macros are available with powered netlists than unpowered netlists.

Configuration Variables¶

Variable Name	Type	Description	Default
`VERILOG_FILES`	List[Path]	The paths of the design’s Verilog files.	`None`
`VERILOG_INCLUDE_DIRS`	List[Path]?	Specifies the Verilog `include` directories.	`None`
`VERILOG_POWER_DEFINE` Deprecated names `SYNTH_USE_PG_PINS_DEFINES` `SYNTH_POWER_DEFINE`	str?	Specifies the name of the define used to guard power and ground connections in the input RTL.	`USE_POWER_PINS`
`LINTER_INCLUDE_PDK_MODELS`	bool	Include Verilog models of the PDK	`False`
`LINTER_RELATIVE_INCLUDES` Deprecated names `VERILATOR_RELATIVE_INCLUDES`	bool	When a file references an include file, resolve the filename relative to the path of the referencing file, instead of relative to the current directory.	`True`
`LINTER_ERROR_ON_LATCH`	bool	When a latch is inferred by an `always` block that is not explicitly marked as `always_latch`, report this as a linter error.	`True`
`LINTER_ERROR_ON_MULTIDRIVEN`	bool	When a net has multiple drivers, report this as a linter error.	`True`
`VERILOG_DEFINES` Deprecated names `SYNTH_DEFINES`	List[str]?	Preprocessor defines for input Verilog files	`None`
`LINTER_DEFINES`	List[str]?	Linter-specific preprocessor definitions; overrides VERILOG_DEFINES for the lint step if exists	`None`
`LINTER_DISABLE_WARNINGS`	List[str]?	Warning codes that are passed to the linter to be disabled.	`['DECLFILENAME', 'EOFNEWLINE']`
`LINTER_DISABLE_WARNINGS_BLACKBOX`	List[str]?	Warning codes that are passed to the linter to be disabled for all blackbox modules.	`['UNDRIVEN', 'UNUSEDSIGNAL']`
`LINTER_VLT`	Path?	Path to a Verilator Configuration format file (`.vlt`) that is passed to the linter.	`None`

Yosys¶

RTL/Netlist Equivalence Check¶

Experimental: Uses the EQY utility to perform an RTL vs. Netlist equivalence check.

Currently, you are expected to provide your own EQY script if you want this to work properly.

Inputs and Outputs¶

Inputs	Outputs
nl (.nl.v)

Configuration Variables¶

Variable Name	Type	Description	Default
`SYNTH_LATCH_MAP` ^PDK	Path?	A path to a file containing the latch mapping for Yosys.	`None`
`SYNTH_TRISTATE_MAP` ^PDK Deprecated names `TRISTATE_BUFFER_MAP`	Path?	A path to a file containing the tri-state buffer mapping for Yosys.	`None`
`SYNTH_CSA_MAP` ^PDK Deprecated names `CARRY_SELECT_ADDER_MAP`	Path?	A path to a file containing the carry-select adder mapping for Yosys.	`None`
`SYNTH_RCA_MAP` ^PDK Deprecated names `RIPPLE_CARRY_ADDER_MAP`	Path?	A path to a file containing the ripple-carry adder mapping for Yosys.	`None`
`SYNTH_FA_MAP` ^PDK Deprecated names `FULL_ADDER_MAP`	Path?	A path to a file containing the full adder mapping for Yosys.	`None`
`SYNTH_MUX_MAP` ^PDK	Path?	A path to a file containing the mux mapping for Yosys.	`None`
`SYNTH_MUX4_MAP` ^PDK	Path?	A path to a file containing the mux4 mapping for Yosys.	`None`
`YOSYS_LOG_LEVEL`	‘ALL’｜ ’WARNING’｜ ’ERROR’	Which log level for Yosys. At WARNING or higher, the initialization splash is also disabled.	`ALL`
`VERILOG_FILES`	List[Path]	The paths of the design’s Verilog files.	`None`
`VERILOG_DEFINES` Deprecated names `SYNTH_DEFINES`	List[str]?	Preprocessor defines for input Verilog files.	`None`
`VERILOG_POWER_DEFINE` Deprecated names `SYNTH_USE_PG_PINS_DEFINES` `SYNTH_POWER_DEFINE`	str?	Specifies the name of the define used to guard power and ground connections in the input RTL.	`USE_POWER_PINS`
`VERILOG_INCLUDE_DIRS`	List[Path]?	Specifies the Verilog `include` directories.	`None`
`SYNTH_PARAMETERS`	List[str]?	Key-value pairs to be `chparam`ed in Yosys, in the format `key1=value1`.	`None`
`USE_SLANG` Deprecated names `USE_SYNLIG`	bool	Use the Slang frontend to process files, which has better SystemVerilog parsing capabilities but is not as battle-tested as the default Yosys friend.	`False`
`SLANG_ARGUMENTS`	List[str]?	Pass arguments to the Slang frontend.	`None`
`EQY_SCRIPT`	Path?	The EQY script to use. If unset, a generic EQY script will be generated, but this fails in a number of scenarios.	`None`
`MACRO_PLACEMENT_CFG`	Path?	This step will warn if this deprecated variable is used, as it indicates Macros are used without the new Macro object.	`None`
`EQY_FORCE_ACCEPT_PDK`	bool	Attempt to run EQY even if the PDK’s Verilog models are supported by this step. Will likely result in a failure.	`False`

Generate JSON Header¶

Extracts a high-level hierarchical view of the circuit in JSON format, including power connections. The power connections are used in later steps to ensure macros and cells are connected as desired.

Inputs and Outputs¶

Inputs	Outputs
	Design JSON Header File (.h.json)

Configuration Variables¶

Variable Name	Type	Description	Default
`SYNTH_LATCH_MAP` ^PDK	Path?	A path to a file containing the latch mapping for Yosys.	`None`
`SYNTH_TRISTATE_MAP` ^PDK Deprecated names `TRISTATE_BUFFER_MAP`	Path?	A path to a file containing the tri-state buffer mapping for Yosys.	`None`
`SYNTH_CSA_MAP` ^PDK Deprecated names `CARRY_SELECT_ADDER_MAP`	Path?	A path to a file containing the carry-select adder mapping for Yosys.	`None`
`SYNTH_RCA_MAP` ^PDK Deprecated names `RIPPLE_CARRY_ADDER_MAP`	Path?	A path to a file containing the ripple-carry adder mapping for Yosys.	`None`
`SYNTH_FA_MAP` ^PDK Deprecated names `FULL_ADDER_MAP`	Path?	A path to a file containing the full adder mapping for Yosys.	`None`
`SYNTH_MUX_MAP` ^PDK	Path?	A path to a file containing the mux mapping for Yosys.	`None`
`SYNTH_MUX4_MAP` ^PDK	Path?	A path to a file containing the mux4 mapping for Yosys.	`None`
`SYNTH_CLOCKGATE_MIN_WIDTH` Deprecated names `USE_LIGHTER`	int?	If set to a value, a group of flip-flops with size >= SYNTH_CLOCKGATE_MIN_WIDTH and an enable signal are clock-gated instead.	`None`
`SYNTH_CLOCKGATE_POSEDGE_ICG` ^PDK	str?	The integrated clock gate cell used for positive-edge flip-flops, in the format `<cell>/<active-high clock enable port>/<clk port>/<gated clk port>`.	`None`
`SYNTH_CLOCKGATE_NEGEDGE_ICG` ^PDK	str?	The integrated clock gate cell used for positive-edge flip-flops, in the format `<cell>/<active-high clock enable port>/<clk port>/<gated clk port>`.	`None`
`YOSYS_LOG_LEVEL`	‘ALL’｜ ’WARNING’｜ ’ERROR’	Which log level for Yosys. At WARNING or higher, the initialization splash is also disabled.	`ALL`
`SYNTH_CORNER` ^PDK	str?	A fully qualified IPVT corner to use during synthesis. If unspecified, the value for `DEFAULT_CORNER` from the PDK will be used.	`None`
`SYNTH_SHOW`	bool	Generate a graphviz DOT file for the design. This will fail on a completely empty design.	`False`
`VERILOG_FILES`	List[Path]	The paths of the design’s Verilog files.	`None`
`VERILOG_DEFINES` Deprecated names `SYNTH_DEFINES`	List[str]?	Preprocessor defines for input Verilog files.	`None`
`VERILOG_POWER_DEFINE` Deprecated names `SYNTH_USE_PG_PINS_DEFINES` `SYNTH_POWER_DEFINE`	str?	Specifies the name of the define used to guard power and ground connections in the input RTL.	`USE_POWER_PINS`
`VERILOG_INCLUDE_DIRS`	List[Path]?	Specifies the Verilog `include` directories.	`None`
`SYNTH_PARAMETERS`	List[str]?	Key-value pairs to be `chparam`ed in Yosys, in the format `key1=value1`.	`None`
`USE_SLANG` Deprecated names `USE_SYNLIG`	bool	Use the Slang frontend to process files, which has better SystemVerilog parsing capabilities but is not as battle-tested as the default Yosys friend.	`False`
`SLANG_ARGUMENTS`	List[str]?	Pass arguments to the Slang frontend.	`None`

Resynthesis¶

Like Synthesis, but operates on the input netlist instead of RTL files. Useful to process/elaborate on netlists generated by tools other than Yosys.

Some metrics will also be extracted and updated, namely:

design__instance__count
design__instance_unmapped__count
design__instance__area

Note that Yosys steps do not currently support gzipped standard cell dotlib files. They are however supported for macros:

https://github.com/YosysHQ/yosys/issues/4830

Inputs and Outputs¶

Inputs	Outputs
nl (.nl.v)	Verilog Netlist (.nl.v)

Configuration Variables¶

Variable Name	Type	Description	Default
`SYNTH_LATCH_MAP` ^PDK	Path?	A path to a file containing the latch mapping for Yosys.	`None`
`SYNTH_TRISTATE_MAP` ^PDK Deprecated names `TRISTATE_BUFFER_MAP`	Path?	A path to a file containing the tri-state buffer mapping for Yosys.	`None`
`SYNTH_CSA_MAP` ^PDK Deprecated names `CARRY_SELECT_ADDER_MAP`	Path?	A path to a file containing the carry-select adder mapping for Yosys.	`None`
`SYNTH_RCA_MAP` ^PDK Deprecated names `RIPPLE_CARRY_ADDER_MAP`	Path?	A path to a file containing the ripple-carry adder mapping for Yosys.	`None`
`SYNTH_FA_MAP` ^PDK Deprecated names `FULL_ADDER_MAP`	Path?	A path to a file containing the full adder mapping for Yosys.	`None`
`SYNTH_MUX_MAP` ^PDK	Path?	A path to a file containing the mux mapping for Yosys.	`None`
`SYNTH_MUX4_MAP` ^PDK	Path?	A path to a file containing the mux4 mapping for Yosys.	`None`
`SYNTH_CLOCKGATE_MIN_WIDTH` Deprecated names `USE_LIGHTER`	int?	If set to a value, a group of flip-flops with size >= SYNTH_CLOCKGATE_MIN_WIDTH and an enable signal are clock-gated instead.	`None`
`SYNTH_CLOCKGATE_POSEDGE_ICG` ^PDK	str?	The integrated clock gate cell used for positive-edge flip-flops, in the format `<cell>/<active-high clock enable port>/<clk port>/<gated clk port>`.	`None`
`SYNTH_CLOCKGATE_NEGEDGE_ICG` ^PDK	str?	The integrated clock gate cell used for positive-edge flip-flops, in the format `<cell>/<active-high clock enable port>/<clk port>/<gated clk port>`.	`None`
`YOSYS_LOG_LEVEL`	‘ALL’｜ ’WARNING’｜ ’ERROR’	Which log level for Yosys. At WARNING or higher, the initialization splash is also disabled.	`ALL`
`SYNTH_CORNER` ^PDK	str?	A fully qualified IPVT corner to use during synthesis. If unspecified, the value for `DEFAULT_CORNER` from the PDK will be used.	`None`
`SYNTH_SHOW`	bool	Generate a graphviz DOT file for the design. This will fail on a completely empty design.	`False`
`SYNTH_CHECKS_ALLOW_TRISTATE`	bool	Ignore multiple-driver warnings if they are connected to tri-state buffers on a best-effort basis.	`True`
`SYNTH_AUTONAME`	bool	Generates names for netlist instances. This results in instance names that can be extremely long, but are more human-readable.	`False`
`SYNTH_STRATEGY`	‘AREA 0’｜ ’AREA 1’｜ ’AREA 2’｜ ’AREA 3’｜ ’DELAY 0’｜ ’DELAY 1’｜ ’DELAY 2’｜ ’DELAY 3’｜ ’DELAY 4’	Strategies for abc logic synthesis and technology mapping. AREA strategies usually result in a more compact design, while DELAY strategies usually result in a design that runs at a higher frequency. Please note that there is no way to know which strategy is the best before trying them.	`AREA 0`
`SYNTH_ABC_BUFFERING` Deprecated names `SYNTH_BUFFERING`	bool	Enables `abc` cell buffering.	`False`
`SYNTH_ABC_LEGACY_REFACTOR`	bool	Replaces the ABC command `drf -l` with `refactor` which matches older versions of LibreLane but is more unstable.	`False`
`SYNTH_ABC_LEGACY_REWRITE`	bool	Replaces the ABC command `drw -l` with `rewrite` which matches older versions of LibreLane but is more unstable.	`False`
`SYNTH_ABC_DFF`	bool	Passes D-flipflop cells through ABC for optimization (which can for example, eliminate identical flip-flops).	`False`
`SYNTH_ABC_USE_MFS3`	bool	Experimental: attempts a SAT-based remapping in all area and delay strategies before ‘retime’, which may improve PPA results.	`False`
`SYNTH_ABC_AREA_USE_NF`	bool	Experimental: uses the &nf delay-based mapper with a very high value instead of the amap area mapper, which may be better in some scenarios at recovering area.	`False`
`SYNTH_DIRECT_WIRE_BUFFERING` Deprecated names `SYNTH_BUFFER_DIRECT_WIRES`	bool	Enables inserting buffer cells for directly connected wires.	`True`
`SYNTH_SPLITNETS`	bool	Splits multi-bit nets into single-bit nets. Easier to trace but may not be supported by all tools.	`True`
`SYNTH_SIZING`	bool	Enables `abc` cell sizing (instead of buffering).	`False`
`SYNTH_HIERARCHY_MODE` Deprecated names `SYNTH_NO_FLAT` `SYNTH_ELABORATE_FLATTEN` `SYNTH_FLAT_TOP`	‘flatten’｜ ’deferred_flatten’｜ ’keep’	Affects how hierarchy is maintained throughout and after synthesis. ‘flatten’ flattens it during and after synthesis. ‘deferred_flatten’ flattens it after synthesis. ‘keep’ never flattens it. Please note that when using the Slang plugin, you need to pass ‘–keep-hierarchy’ to `SLANG_ARGUMENTS` separately. To keep the hierarchy partially, use one of the flattening options and set the ‘keep_hierarchy’ attribute on instances or modules via: `SYNTH_KEEP_HIERARCHY_INSTANCES`, `SYNTH_KEEP_HIERARCHY_MODULES` or `SYNTH_KEEP_HIERARCHY_MIN_COST`.	`flatten`
`SYNTH_KEEP_HIERARCHY_MIN_COST`	int?	Sets the ‘keep_hierarchy’ attribute on modules where the gate count is estimated to exceed the specified threshold. This prevents larger modules from being flattened. This variable only affects the design when ‘flatten’ is called through `SYNTH_HIERARCHY_MODE`.	`None`
`SYNTH_KEEP_HIERARCHY_INSTANCES`	List[str]?	A list of instances for which to set the ‘keep_hierarchy’ attribute. This variable only affects the design when ‘flatten’ is called through `SYNTH_HIERARCHY_MODE`.	`None`
`SYNTH_KEEP_HIERARCHY_MODULES`	List[str]?	A list of modules for which to set the ‘keep_hierarchy’ attribute. This variable only affects the design when ‘flatten’ is called through `SYNTH_HIERARCHY_MODE`.	`None`
`SYNTH_SHARE_RESOURCES`	bool	A flag that enables yosys to reduce the number of cells by determining shareable resources and merging them.	`True`
`SYNTH_ADDER_TYPE`	‘YOSYS’｜ ’FA’｜ ’RCA’｜ ’CSA’	Adder type to which the $add and $sub operators are mapped to. Possible values are `YOSYS/FA/RCA/CSA`; where `YOSYS` refers to using Yosys internal adder definition, `FA` refers to full-adder structure, `RCA` refers to ripple carry adder structure, and `CSA` refers to carry select adder.	`YOSYS`
`SYNTH_EXTRA_MAPPING_FILE`	Path?	Points to an extra techmap file for yosys that runs right after yosys `synth` before generic techmap.	`None`
`SYNTH_ELABORATE_ONLY`	bool	“Elaborate” the design only without attempting any logic mapping. Useful when dealing with structural Verilog netlists.	`False`
`SYNTH_MUL_BOOTH`	bool	Runs the booth pass as part of synthesis: See https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/booth.html	`False`
`SYNTH_TIE_UNDEFINED`	‘high’｜ ’low’	Whether to tie undefined values low or high. Explicitly provide null if you wish to simply leave them undriven.	`low`
`SYNTH_WRITE_NOATTR`	bool	If true, Verilog-2001 attributes are omitted from output netlists. Some utilities do not support attributes.	`True`
`SYNTH_NORMALIZE_SINGLE_BIT_VECTORS`	bool	If true, vectors with the shape [0:0] are converted to normal wires in the netlist. If disabled, even one-width pins will be suffixed [0] in the layout when imported by most PnR tools.	`True`

Synthesis¶

Performs synthesis and technology mapping on Verilog RTL files using Yosys and ABC, emitting a netlist.

Some metrics will also be extracted and updated, namely:

design__instance__count
design__instance_unmapped__count
design__instance__area

Note that Yosys steps do not currently support gzipped standard cell dotlib files. They are however supported for macros:

https://github.com/YosysHQ/yosys/issues/4830

Inputs and Outputs¶

Inputs	Outputs
	Verilog Netlist (.nl.v)

Configuration Variables¶

Variable Name	Type	Description	Default
`SYNTH_LATCH_MAP` ^PDK	Path?	A path to a file containing the latch mapping for Yosys.	`None`
`SYNTH_TRISTATE_MAP` ^PDK Deprecated names `TRISTATE_BUFFER_MAP`	Path?	A path to a file containing the tri-state buffer mapping for Yosys.	`None`
`SYNTH_CSA_MAP` ^PDK Deprecated names `CARRY_SELECT_ADDER_MAP`	Path?	A path to a file containing the carry-select adder mapping for Yosys.	`None`
`SYNTH_RCA_MAP` ^PDK Deprecated names `RIPPLE_CARRY_ADDER_MAP`	Path?	A path to a file containing the ripple-carry adder mapping for Yosys.	`None`
`SYNTH_FA_MAP` ^PDK Deprecated names `FULL_ADDER_MAP`	Path?	A path to a file containing the full adder mapping for Yosys.	`None`
`SYNTH_MUX_MAP` ^PDK	Path?	A path to a file containing the mux mapping for Yosys.	`None`
`SYNTH_MUX4_MAP` ^PDK	Path?	A path to a file containing the mux4 mapping for Yosys.	`None`
`SYNTH_CLOCKGATE_MIN_WIDTH` Deprecated names `USE_LIGHTER`	int?	If set to a value, a group of flip-flops with size >= SYNTH_CLOCKGATE_MIN_WIDTH and an enable signal are clock-gated instead.	`None`
`SYNTH_CLOCKGATE_POSEDGE_ICG` ^PDK	str?	The integrated clock gate cell used for positive-edge flip-flops, in the format `<cell>/<active-high clock enable port>/<clk port>/<gated clk port>`.	`None`
`SYNTH_CLOCKGATE_NEGEDGE_ICG` ^PDK	str?	The integrated clock gate cell used for positive-edge flip-flops, in the format `<cell>/<active-high clock enable port>/<clk port>/<gated clk port>`.	`None`
`YOSYS_LOG_LEVEL`	‘ALL’｜ ’WARNING’｜ ’ERROR’	Which log level for Yosys. At WARNING or higher, the initialization splash is also disabled.	`ALL`
`SYNTH_CORNER` ^PDK	str?	A fully qualified IPVT corner to use during synthesis. If unspecified, the value for `DEFAULT_CORNER` from the PDK will be used.	`None`
`SYNTH_SHOW`	bool	Generate a graphviz DOT file for the design. This will fail on a completely empty design.	`False`
`SYNTH_CHECKS_ALLOW_TRISTATE`	bool	Ignore multiple-driver warnings if they are connected to tri-state buffers on a best-effort basis.	`True`
`SYNTH_AUTONAME`	bool	Generates names for netlist instances. This results in instance names that can be extremely long, but are more human-readable.	`False`
`SYNTH_STRATEGY`	‘AREA 0’｜ ’AREA 1’｜ ’AREA 2’｜ ’AREA 3’｜ ’DELAY 0’｜ ’DELAY 1’｜ ’DELAY 2’｜ ’DELAY 3’｜ ’DELAY 4’	Strategies for abc logic synthesis and technology mapping. AREA strategies usually result in a more compact design, while DELAY strategies usually result in a design that runs at a higher frequency. Please note that there is no way to know which strategy is the best before trying them.	`AREA 0`
`SYNTH_ABC_BUFFERING` Deprecated names `SYNTH_BUFFERING`	bool	Enables `abc` cell buffering.	`False`
`SYNTH_ABC_LEGACY_REFACTOR`	bool	Replaces the ABC command `drf -l` with `refactor` which matches older versions of LibreLane but is more unstable.	`False`
`SYNTH_ABC_LEGACY_REWRITE`	bool	Replaces the ABC command `drw -l` with `rewrite` which matches older versions of LibreLane but is more unstable.	`False`
`SYNTH_ABC_DFF`	bool	Passes D-flipflop cells through ABC for optimization (which can for example, eliminate identical flip-flops).	`False`
`SYNTH_ABC_USE_MFS3`	bool	Experimental: attempts a SAT-based remapping in all area and delay strategies before ‘retime’, which may improve PPA results.	`False`
`SYNTH_ABC_AREA_USE_NF`	bool	Experimental: uses the &nf delay-based mapper with a very high value instead of the amap area mapper, which may be better in some scenarios at recovering area.	`False`
`SYNTH_DIRECT_WIRE_BUFFERING` Deprecated names `SYNTH_BUFFER_DIRECT_WIRES`	bool	Enables inserting buffer cells for directly connected wires.	`True`
`SYNTH_SPLITNETS`	bool	Splits multi-bit nets into single-bit nets. Easier to trace but may not be supported by all tools.	`True`
`SYNTH_SIZING`	bool	Enables `abc` cell sizing (instead of buffering).	`False`
`SYNTH_HIERARCHY_MODE` Deprecated names `SYNTH_NO_FLAT` `SYNTH_ELABORATE_FLATTEN` `SYNTH_FLAT_TOP`	‘flatten’｜ ’deferred_flatten’｜ ’keep’	Affects how hierarchy is maintained throughout and after synthesis. ‘flatten’ flattens it during and after synthesis. ‘deferred_flatten’ flattens it after synthesis. ‘keep’ never flattens it. Please note that when using the Slang plugin, you need to pass ‘–keep-hierarchy’ to `SLANG_ARGUMENTS` separately. To keep the hierarchy partially, use one of the flattening options and set the ‘keep_hierarchy’ attribute on instances or modules via: `SYNTH_KEEP_HIERARCHY_INSTANCES`, `SYNTH_KEEP_HIERARCHY_MODULES` or `SYNTH_KEEP_HIERARCHY_MIN_COST`.	`flatten`
`SYNTH_KEEP_HIERARCHY_MIN_COST`	int?	Sets the ‘keep_hierarchy’ attribute on modules where the gate count is estimated to exceed the specified threshold. This prevents larger modules from being flattened. This variable only affects the design when ‘flatten’ is called through `SYNTH_HIERARCHY_MODE`.	`None`
`SYNTH_KEEP_HIERARCHY_INSTANCES`	List[str]?	A list of instances for which to set the ‘keep_hierarchy’ attribute. This variable only affects the design when ‘flatten’ is called through `SYNTH_HIERARCHY_MODE`.	`None`
`SYNTH_KEEP_HIERARCHY_MODULES`	List[str]?	A list of modules for which to set the ‘keep_hierarchy’ attribute. This variable only affects the design when ‘flatten’ is called through `SYNTH_HIERARCHY_MODE`.	`None`
`SYNTH_SHARE_RESOURCES`	bool	A flag that enables yosys to reduce the number of cells by determining shareable resources and merging them.	`True`
`SYNTH_ADDER_TYPE`	‘YOSYS’｜ ’FA’｜ ’RCA’｜ ’CSA’	Adder type to which the $add and $sub operators are mapped to. Possible values are `YOSYS/FA/RCA/CSA`; where `YOSYS` refers to using Yosys internal adder definition, `FA` refers to full-adder structure, `RCA` refers to ripple carry adder structure, and `CSA` refers to carry select adder.	`YOSYS`
`SYNTH_EXTRA_MAPPING_FILE`	Path?	Points to an extra techmap file for yosys that runs right after yosys `synth` before generic techmap.	`None`
`SYNTH_ELABORATE_ONLY`	bool	“Elaborate” the design only without attempting any logic mapping. Useful when dealing with structural Verilog netlists.	`False`
`SYNTH_MUL_BOOTH`	bool	Runs the booth pass as part of synthesis: See https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/booth.html	`False`
`SYNTH_TIE_UNDEFINED`	‘high’｜ ’low’	Whether to tie undefined values low or high. Explicitly provide null if you wish to simply leave them undriven.	`low`
`SYNTH_WRITE_NOATTR`	bool	If true, Verilog-2001 attributes are omitted from output netlists. Some utilities do not support attributes.	`True`
`SYNTH_NORMALIZE_SINGLE_BIT_VECTORS`	bool	If true, vectors with the shape [0:0] are converted to normal wires in the netlist. If disabled, even one-width pins will be suffixed [0] in the layout when imported by most PnR tools.	`True`
`VERILOG_FILES`	List[Path]	The paths of the design’s Verilog files.	`None`
`VERILOG_DEFINES` Deprecated names `SYNTH_DEFINES`	List[str]?	Preprocessor defines for input Verilog files.	`None`
`VERILOG_POWER_DEFINE` Deprecated names `SYNTH_USE_PG_PINS_DEFINES` `SYNTH_POWER_DEFINE`	str?	Specifies the name of the define used to guard power and ground connections in the input RTL.	`USE_POWER_PINS`
`VERILOG_INCLUDE_DIRS`	List[Path]?	Specifies the Verilog `include` directories.	`None`
`SYNTH_PARAMETERS`	List[str]?	Key-value pairs to be `chparam`ed in Yosys, in the format `key1=value1`.	`None`
`USE_SLANG` Deprecated names `USE_SYNLIG`	bool	Use the Slang frontend to process files, which has better SystemVerilog parsing capabilities but is not as battle-tested as the default Yosys friend.	`False`
`SLANG_ARGUMENTS`	List[str]?	Pass arguments to the Slang frontend.	`None`

Synthesis (VHDL)¶

Performs synthesis and technology mapping on VHDL files using Yosys, GHDL and ABC, emitting a netlist.

Some metrics will also be extracted and updated, namely:

design__instance__count
design__instance_unmapped__count
design__instance__area

Note that Yosys steps do not currently support gzipped standard cell dotlib files. They are however supported for macros:

https://github.com/YosysHQ/yosys/issues/4830

Inputs and Outputs¶

Inputs	Outputs
	Verilog Netlist (.nl.v)

Configuration Variables¶

Variable Name	Type	Description	Default
`SYNTH_LATCH_MAP` ^PDK	Path?	A path to a file containing the latch mapping for Yosys.	`None`
`SYNTH_TRISTATE_MAP` ^PDK Deprecated names `TRISTATE_BUFFER_MAP`	Path?	A path to a file containing the tri-state buffer mapping for Yosys.	`None`
`SYNTH_CSA_MAP` ^PDK Deprecated names `CARRY_SELECT_ADDER_MAP`	Path?	A path to a file containing the carry-select adder mapping for Yosys.	`None`
`SYNTH_RCA_MAP` ^PDK Deprecated names `RIPPLE_CARRY_ADDER_MAP`	Path?	A path to a file containing the ripple-carry adder mapping for Yosys.	`None`
`SYNTH_FA_MAP` ^PDK Deprecated names `FULL_ADDER_MAP`	Path?	A path to a file containing the full adder mapping for Yosys.	`None`
`SYNTH_MUX_MAP` ^PDK	Path?	A path to a file containing the mux mapping for Yosys.	`None`
`SYNTH_MUX4_MAP` ^PDK	Path?	A path to a file containing the mux4 mapping for Yosys.	`None`
`SYNTH_CLOCKGATE_MIN_WIDTH` Deprecated names `USE_LIGHTER`	int?	If set to a value, a group of flip-flops with size >= SYNTH_CLOCKGATE_MIN_WIDTH and an enable signal are clock-gated instead.	`None`
`SYNTH_CLOCKGATE_POSEDGE_ICG` ^PDK	str?	The integrated clock gate cell used for positive-edge flip-flops, in the format `<cell>/<active-high clock enable port>/<clk port>/<gated clk port>`.	`None`
`SYNTH_CLOCKGATE_NEGEDGE_ICG` ^PDK	str?	The integrated clock gate cell used for positive-edge flip-flops, in the format `<cell>/<active-high clock enable port>/<clk port>/<gated clk port>`.	`None`
`YOSYS_LOG_LEVEL`	‘ALL’｜ ’WARNING’｜ ’ERROR’	Which log level for Yosys. At WARNING or higher, the initialization splash is also disabled.	`ALL`
`SYNTH_CORNER` ^PDK	str?	A fully qualified IPVT corner to use during synthesis. If unspecified, the value for `DEFAULT_CORNER` from the PDK will be used.	`None`
`SYNTH_SHOW`	bool	Generate a graphviz DOT file for the design. This will fail on a completely empty design.	`False`
`SYNTH_CHECKS_ALLOW_TRISTATE`	bool	Ignore multiple-driver warnings if they are connected to tri-state buffers on a best-effort basis.	`True`
`SYNTH_AUTONAME`	bool	Generates names for netlist instances. This results in instance names that can be extremely long, but are more human-readable.	`False`
`SYNTH_STRATEGY`	‘AREA 0’｜ ’AREA 1’｜ ’AREA 2’｜ ’AREA 3’｜ ’DELAY 0’｜ ’DELAY 1’｜ ’DELAY 2’｜ ’DELAY 3’｜ ’DELAY 4’	Strategies for abc logic synthesis and technology mapping. AREA strategies usually result in a more compact design, while DELAY strategies usually result in a design that runs at a higher frequency. Please note that there is no way to know which strategy is the best before trying them.	`AREA 0`
`SYNTH_ABC_BUFFERING` Deprecated names `SYNTH_BUFFERING`	bool	Enables `abc` cell buffering.	`False`
`SYNTH_ABC_LEGACY_REFACTOR`	bool	Replaces the ABC command `drf -l` with `refactor` which matches older versions of LibreLane but is more unstable.	`False`
`SYNTH_ABC_LEGACY_REWRITE`	bool	Replaces the ABC command `drw -l` with `rewrite` which matches older versions of LibreLane but is more unstable.	`False`
`SYNTH_ABC_DFF`	bool	Passes D-flipflop cells through ABC for optimization (which can for example, eliminate identical flip-flops).	`False`
`SYNTH_ABC_USE_MFS3`	bool	Experimental: attempts a SAT-based remapping in all area and delay strategies before ‘retime’, which may improve PPA results.	`False`
`SYNTH_ABC_AREA_USE_NF`	bool	Experimental: uses the &nf delay-based mapper with a very high value instead of the amap area mapper, which may be better in some scenarios at recovering area.	`False`
`SYNTH_DIRECT_WIRE_BUFFERING` Deprecated names `SYNTH_BUFFER_DIRECT_WIRES`	bool	Enables inserting buffer cells for directly connected wires.	`True`
`SYNTH_SPLITNETS`	bool	Splits multi-bit nets into single-bit nets. Easier to trace but may not be supported by all tools.	`True`
`SYNTH_SIZING`	bool	Enables `abc` cell sizing (instead of buffering).	`False`
`SYNTH_HIERARCHY_MODE` Deprecated names `SYNTH_NO_FLAT` `SYNTH_ELABORATE_FLATTEN` `SYNTH_FLAT_TOP`	‘flatten’｜ ’deferred_flatten’｜ ’keep’	Affects how hierarchy is maintained throughout and after synthesis. ‘flatten’ flattens it during and after synthesis. ‘deferred_flatten’ flattens it after synthesis. ‘keep’ never flattens it. Please note that when using the Slang plugin, you need to pass ‘–keep-hierarchy’ to `SLANG_ARGUMENTS` separately. To keep the hierarchy partially, use one of the flattening options and set the ‘keep_hierarchy’ attribute on instances or modules via: `SYNTH_KEEP_HIERARCHY_INSTANCES`, `SYNTH_KEEP_HIERARCHY_MODULES` or `SYNTH_KEEP_HIERARCHY_MIN_COST`.	`flatten`
`SYNTH_KEEP_HIERARCHY_MIN_COST`	int?	Sets the ‘keep_hierarchy’ attribute on modules where the gate count is estimated to exceed the specified threshold. This prevents larger modules from being flattened. This variable only affects the design when ‘flatten’ is called through `SYNTH_HIERARCHY_MODE`.	`None`
`SYNTH_KEEP_HIERARCHY_INSTANCES`	List[str]?	A list of instances for which to set the ‘keep_hierarchy’ attribute. This variable only affects the design when ‘flatten’ is called through `SYNTH_HIERARCHY_MODE`.	`None`
`SYNTH_KEEP_HIERARCHY_MODULES`	List[str]?	A list of modules for which to set the ‘keep_hierarchy’ attribute. This variable only affects the design when ‘flatten’ is called through `SYNTH_HIERARCHY_MODE`.	`None`
`SYNTH_SHARE_RESOURCES`	bool	A flag that enables yosys to reduce the number of cells by determining shareable resources and merging them.	`True`
`SYNTH_ADDER_TYPE`	‘YOSYS’｜ ’FA’｜ ’RCA’｜ ’CSA’	Adder type to which the $add and $sub operators are mapped to. Possible values are `YOSYS/FA/RCA/CSA`; where `YOSYS` refers to using Yosys internal adder definition, `FA` refers to full-adder structure, `RCA` refers to ripple carry adder structure, and `CSA` refers to carry select adder.	`YOSYS`
`SYNTH_EXTRA_MAPPING_FILE`	Path?	Points to an extra techmap file for yosys that runs right after yosys `synth` before generic techmap.	`None`
`SYNTH_ELABORATE_ONLY`	bool	“Elaborate” the design only without attempting any logic mapping. Useful when dealing with structural Verilog netlists.	`False`
`SYNTH_MUL_BOOTH`	bool	Runs the booth pass as part of synthesis: See https://yosyshq.readthedocs.io/projects/yosys/en/latest/cmd/booth.html	`False`
`SYNTH_TIE_UNDEFINED`	‘high’｜ ’low’	Whether to tie undefined values low or high. Explicitly provide null if you wish to simply leave them undriven.	`low`
`SYNTH_WRITE_NOATTR`	bool	If true, Verilog-2001 attributes are omitted from output netlists. Some utilities do not support attributes.	`True`
`SYNTH_NORMALIZE_SINGLE_BIT_VECTORS`	bool	If true, vectors with the shape [0:0] are converted to normal wires in the netlist. If disabled, even one-width pins will be suffixed [0] in the layout when imported by most PnR tools.	`True`
`VHDL_FILES`	List[Path]	The paths of the design’s VHDL files.	`None`
`GHDL_ARGUMENTS`	List[str]?	Pass arguments to the ghdl frontend.	`None`

Misc¶

Load Base Design Constraints File¶

Loads an SDC file specified as a configuration variable into the state object unaltered.

This Step exists for legacy compatibility and should not be used in new flows.

Inputs and Outputs¶

Inputs	Outputs
	Design Constraints (.sdc)

Report Manufacturability (DRC, LVS, Antenna)¶

Logs a simple “manufacturability report”, i.e., the status of DRC, LVS, and antenna violations.