Option 2 — Full-Wrapper Flattening strategy¶

Note

We’re assuming your RTL files still have the modifications from Option 1.

Please follow Option 1 first if you haven’t already.

In this strategy, we will harden the user_project_wrapper with the aes as one large flattened macro.

Configuration¶

Since we will only harden the user_project_wrapper. Only the librelane/user_project_wrapper/config.json will be edited. The following edits are needed for the user_project_wrapper

Add the AES Verilog files

    "VERILOG_FILES": [
        "dir::../../../secworks_aes/src/rtl/*.v",
        "dir::../../verilog/rtl/aes_wb_wrapper.v",
        "dir::../../verilog/rtl/defines.v",
        "dir::../../verilog/rtl/user_project_wrapper.v"
    ],

Remove the Macros configurations section as there will not be any macros
Update the hardening strategy part to the flattened version

    "//": "Hardening strategy variables (this is for 2-Full-Wrapper Flattening). Visit https://docs.google.com/document/d/1pf-wbpgjeNEM-1TcvX2OJTkHjqH_C9p-LURCASS0Zo8 for more info",
    "SYNTH_ELABORATE_ONLY": false,
    "RUN_POST_GPL_DESIGN_REPAIR": true,
    "RUN_POST_CTS_RESIZER_TIMING": true,
    "DESIGN_REPAIR_BUFFER_INPUT_PORTS": true,
    "PDN_ENABLE_RAILS": true,
    "RUN_ANTENNA_REPAIR": true,
    "RUN_FILL_INSERTION": true,
    "RUN_TAP_ENDCAP_INSERTION": true,
    "RUN_CTS": true,
    "RUN_IRDROP_REPORT": true,
    "VSRC_LOC_FILES": {
        "vccd1": "dir::vsrc/upw_vccd1_vsrc.loc",
        "vssd1": "dir::vsrc/upw_vssd1_vsrc.loc"
    },

Now the full configuration file will be:

Running the flow and dealing with the synthesis checks¶

To harden macros with LibreLane, we use the default flow, Classic.

[nix-shell:~/librelane]$ librelane ~/caravel_aes_accelerator/openlane/user_project_wrapper/config.json

This time however, the flow will stop shortly after synthesis with the message 207 Yosys check errors found..

Synthesis checks are reported in two files that both exist in xx-yosys-synthesis:

reports/pre_synth_chk.rpt
reports/chk.rpt

If you investigate, these files, you’ll run into these errors:

28. Executing CHECK pass (checking for obvious problems).
Checking module user_project_wrapper...
Warning: Wire user_project_wrapper.\la_data_out [127] is used but has no driver.
…
Warning: Wire user_project_wrapper.\io_out [37] is used but has no driver.
…
Warning: Wire user_project_wrapper.\io_oeb [37] is used but has no driver.
…
Warning: Wire user_project_wrapper.\user_irq [2] is used but has no driver.
…

As we’re performing full synthesis and not simple elaboration on the wrapper like in Option 1, Yosys checks a very crucial element of our design: we need to ensure that all outputs are driven.

In this case, you may simply add these lines to verilog/rtl/user_project_wrapper.v:

assign io_out = {`MPRJ_IO_PADS{1'b0}};
assign io_oeb = {`MPRJ_IO_PADS{1'b0}};
assign la_data_out = 128'b0;
assign user_irq = 3'b0;

Then simply re-run the flow.

[nix-shell:~/librelane]$ librelane ~/caravel_aes_accelerator/openlane/user_project_wrapper/config.json

The flow will finish successfully in ~1-2 hours and we will see:

Flow complete.

Viewing the layout¶

To open the final GDSII layout run this command:

[nix-shell:~/librelane]$ librelane --last-run --flow openinklayout ~/caravel_aes_accelerator/openlane/user_project_wrapper/config.json

Now, we can see that there are STD cells all over the user_project_wrapper without any macros. Also, we can see that the logic is clustered in the bottom left corner close to the Wishbone bus.

../../../_images/mprj-flattened-1.webp — Fig. 30 Final layout of the user_project_wrapper after flattening¶

Checking the reports¶

`OpenROAD.CheckAntennas`¶

Once again, with LibreLane ≥ 3.0.0, there should be no antenna violations.

In the event they do appear though, the same strategy as [](./

`OpenROAD.STAPostPnR`¶

Looking at xx-openroad-stapostpnr/summary.rpt, there are multiple max Slew/Cap violations and 1 hold violation which is not Reg to Reg.

┏━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━┳━━━━━━━━━━┳━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━┳━━━━━━━━━━━┳━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━┓
┃              ┃ Hold Worst   ┃ Reg to Reg   ┃          ┃ Hold         ┃ of which Reg ┃ Setup Worst   ┃ Reg to Reg   ┃           ┃ Setup         ┃ of which Reg ┃ Max Cap       ┃ Max Slew     ┃
┃ Corner/Group ┃ Slack        ┃ Paths        ┃ Hold TNS ┃ Violations   ┃ to Reg       ┃ Slack         ┃ Paths        ┃ Setup TNS ┃ Violations    ┃ to Reg       ┃ Violations    ┃ Violations   ┃
┡━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━╇━━━━━━━━━━╇━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━╇━━━━━━━━━━━╇━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━┩
│ Overall      │ -0.0108      │ 0.1068       │ -0.0108  │ 1            │ 0            │ 5.1907        │ 5.1907       │ 0.0000    │ 0             │ 0            │ 44            │ 275          │
│ nom_tt_025C… │ 0.1236       │ 0.3212       │ 0.0000   │ 0            │ 0            │ 11.2213       │ 15.3832      │ 0.0000    │ 0             │ 0            │ 1             │ 4            │
│ nom_ss_100C… │ 0.4500       │ 0.8885       │ 0.0000   │ 0            │ 0            │ 5.7475        │ 5.7475       │ 0.0000    │ 0             │ 0            │ 38            │ 235          │
│ nom_ff_n40C… │ 0.0365       │ 0.1079       │ 0.0000   │ 0            │ 0            │ 11.1783       │ 18.8282      │ 0.0000    │ 0             │ 0            │ 0             │ 0            │
│ min_tt_025C… │ 0.1726       │ 0.3196       │ 0.0000   │ 0            │ 0            │ 11.2516       │ 15.6835      │ 0.0000    │ 0             │ 0            │ 1             │ 1            │
│ min_ss_100C… │ 0.5527       │ 0.8798       │ 0.0000   │ 0            │ 0            │ 6.2822        │ 6.2822       │ 0.0000    │ 0             │ 0            │ 29            │ 168          │
│ min_ff_n40C… │ 0.0791       │ 0.1068       │ 0.0000   │ 0            │ 0            │ 11.2090       │ 19.0602      │ 0.0000    │ 0             │ 0            │ 0             │ 0            │
│ max_tt_025C… │ 0.0536       │ 0.3234       │ 0.0000   │ 0            │ 0            │ 11.1886       │ 15.0609      │ 0.0000    │ 0             │ 0            │ 5             │ 25           │
│ max_ss_100C… │ 0.3233       │ 0.8972       │ 0.0000   │ 0            │ 0            │ 5.1907        │ 5.1907       │ 0.0000    │ 0             │ 0            │ 44            │ 275          │
│ max_ff_n40C… │ -0.0108      │ 0.1095       │ -0.0108  │ 1            │ 0            │ 11.1440       │ 18.5834      │ 0.0000    │ 0             │ 0            │ 0             │ 0            │
└──────────────┴──────────────┴──────────────┴──────────┴──────────────┴──────────────┴───────────────┴──────────────┴───────────┴───────────────┴──────────────┴───────────────┴──────────────┘

The max Slew/Cap violations can be fixed the same way as in this section. For the hold violation, it is in the max_ff_n40C_1v95 corner. To investigate the timing path, open the report xx-openroad-stapostpnr/max_ff_n40C_1v95/min.rpt and the violation will be in the first timing path.

Note

There might be more hold violations or no violations at all depending on the version of LibreLane being used as this is a violation with a very small negative slack and the results can slightly change with LibreLane or OpenROAD updates.

To fix hold violations, one or more of the following solutions can be applied:

Enable post-global routing timing optimizations using RUN_POST_GRT_RESIZER_TIMING:

    "RUN_POST_GRT_RESIZER_TIMING": true,

Increase the hold repair margins using PL_RESIZER_HOLD_SLACK_MARGIN and GRT_RESIZER_HOLD_SLACK_MARGIN. The default values are 0.1ns and 0.05ns. We can increase those as follows:

    "PL_RESIZER_HOLD_SLACK_MARGIN": 0.2,
    "GRT_RESIZER_HOLD_SLACK_MARGIN": 0.2,

Change the default timing corner using DEFAULT_CORNER:

    "DEFAULT_CORNER": "max_tt_025C_1v80",

Most importantly, it is recommended to use a specific constraint file for your design using PNR_SDC_FILE and SIGNOFF_SDC_FILE

    "PNR_SDC_FILE": "dir::cons.sdc",
    "SIGNOFF_SDC_FILE": "dir::cons.sdc",

`Magic.DRC`¶

Under the directory xx-magic-drc, you will find a file named reports/drc.rpt that summarizes the DRC violations reported by magic. The design is DRC clean so the report will look like this:

aes_wb_wrapper
----------------------------------------
[INFO] COUNT: 0
[INFO] Should be divided by 3 or 4

`KLayout.DRC`¶

Under the directory xx-klayout-drc, you will find a file named violations.json that summarizes the DRC violations reported by KLayout. The design is DRC clean so the report will look like this with "total": 0 at the end:

{
  ⋮
  "total": 0
}

`Netgen.LVS`¶

Under the directory xx-netgen-lvs, you will find a file named lvs.rpt that summarizes the LVS violations reported by Netgen. The design is LVS clean so the last part of the report will look like this:

Cell pin lists are equivalent.
Device classes user_project_wrapper and user_project_wrapper are equivalent.

Final result: Circuits match uniquely.

Re-running the flow with a modified configuration¶

To fix the previous issues in the implementation, the following was added to the user_project_wrapper config file:

    "//": "New variables",
    "DEFAULT_CORNER": "max_tt_025C_1v80",
    "RUN_POST_GRT_DESIGN_REPAIR": true,
    "RUN_POST_GRT_RESIZER_TIMING": true,

and the following constraints file pnr.sdc was created at ~/caravel_aes_accelerator/openlane/user_project_wrapper/. This file is originally copied from ~/caravel_aes_accelerator/openlane/user_project_wrapper/signoff.sdc and edited to fix the transition and hold violations:

pnr.sdc

# Copied from signoff.sdc then edited

## Note:
# - input clock transition and latency are set for wb_clk_i port.
#   If your design is using the user_clock2, update the clock constraints to reflect that and use usr_* variables.
# - IO ports are assumed to be asynchronous. If they're synchronous to the clock, update the variable IO_SYNC to 1.
#   As well, update in_ext_delay and out_ext_delay with the required I/O external delays.

#------------------------------------------#
# Pre-defined Constraints
#------------------------------------------#

set ::env(IO_SYNC) 0
# Clock network
if {[info exists ::env(CLOCK_PORT)] && $::env(CLOCK_PORT) != ""} {
    set clk_input $::env(CLOCK_PORT)
    create_clock [get_ports $clk_input] -name clk -period $::env(CLOCK_PERIOD)
    puts "\[INFO\]: Creating clock {clk} for port $clk_input with period: $::env(CLOCK_PERIOD)"
} else {
    set clk_input __VIRTUAL_CLK__
    create_clock -name clk -period $::env(CLOCK_PERIOD)
    puts "\[INFO\]: Creating virtual clock with period: $::env(CLOCK_PERIOD)"
}
if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL)] } {
    set ::env(SYNTH_CLK_DRIVING_CELL) $::env(SYNTH_DRIVING_CELL)
}
if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL_PIN)] } {
    set ::env(SYNTH_CLK_DRIVING_CELL_PIN) $::env(SYNTH_DRIVING_CELL_PIN)
}

# Clock non-idealities
set_propagated_clock [all_clocks]
set_clock_uncertainty 0.15 [get_clocks {clk}]
puts "\[INFO\]: Setting clock uncertainty to: 0.15"
set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clk}]
puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"

# Maximum transition time for the design nets
set_max_transition 0.75 [current_design]
puts "\[INFO\]: Setting maximum transition to: 0.75"

# Maximum fanout
set_max_fanout 16 [current_design]
puts "\[INFO\]: Setting maximum fanout to: 16"

# Timing paths delays derate
set_timing_derate -early [expr {1-0.07}]
set_timing_derate -late [expr {1+0.07}]
puts "\[INFO\]: Setting timing derate to: [expr {0.07 * 100}] %"

# Reset input delay
set_input_delay [expr $::env(CLOCK_PERIOD) * 0.5] -clock [get_clocks {clk}] [get_ports {wb_rst_i}]

# Multicycle paths
set_multicycle_path -setup 2 -through [get_ports {wbs_ack_o}]
set_multicycle_path -hold 1  -through [get_ports {wbs_ack_o}]
set_multicycle_path -setup 2 -through [get_ports {wbs_cyc_i}]
set_multicycle_path -hold 1  -through [get_ports {wbs_cyc_i}]
set_multicycle_path -setup 2 -through [get_ports {wbs_stb_i}]
set_multicycle_path -hold 1  -through [get_ports {wbs_stb_i}]

#------------------------------------------#
# Retrieved Constraints
#------------------------------------------#

# Clock source latency
set usr_clk_max_latency 4.57
set usr_clk_min_latency 4.11
set clk_max_latency 5.57
set clk_min_latency 4.65
set_clock_latency -source -max $clk_max_latency [get_clocks {clk}]
set_clock_latency -source -min $clk_min_latency [get_clocks {clk}]
puts "\[INFO\]: Setting clock latency range: $clk_min_latency : $clk_max_latency"

# Clock input Transition
set usr_clk_tran 0.13
set clk_tran 0.61
set_input_transition $clk_tran [get_ports $clk_input]
puts "\[INFO\]: Setting clock transition: $clk_tran"

# Input delays
set_input_delay -max 1.87 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
set_input_delay -max 1.89 -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
set_input_delay -max 3.17 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
set_input_delay -max 3.74 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
set_input_delay -max 3.89 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
set_input_delay -max 4.13 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
set_input_delay -max 4.61 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
set_input_delay -max 4.74 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
set_input_delay -min 0.18 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
set_input_delay -min 0.3  -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
set_input_delay -min 0.79 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
# wbs_dat_i minimum input delay was decreased here to fix hold violations
set_input_delay -min 0.80 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
set_input_delay -min 1.19 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
set_input_delay -min 1.65 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
set_input_delay -min 1.69 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
set_input_delay -min 1.86 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
if { $::env(IO_SYNC) } {
    set in_ext_delay 4
    puts "\[INFO\]: Setting input ports external delay to: $in_ext_delay"
    set_input_delay -max [expr $in_ext_delay + 4.55] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
    set_input_delay -min [expr $in_ext_delay + 1.26] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
}

# Input Transition
set_input_transition -max 0.14  [get_ports {wbs_we_i}]
set_input_transition -max 0.15  [get_ports {wbs_stb_i}]
set_input_transition -max 0.17  [get_ports {wbs_cyc_i}]
set_input_transition -max 0.18  [get_ports {wbs_sel_i[*]}]
set_input_transition -max 0.38  [get_ports {io_in[*]}]
set_input_transition -max 0.84  [get_ports {wbs_dat_i[*]}]
set_input_transition -max 0.86  [get_ports {la_data_in[*]}]
set_input_transition -max 0.92  [get_ports {wbs_adr_i[*]}]
set_input_transition -max 0.97  [get_ports {la_oenb[*]}]
set_input_transition -min 0.05  [get_ports {io_in[*]}]
set_input_transition -min 0.06  [get_ports {la_oenb[*]}]
set_input_transition -min 0.07  [get_ports {la_data_in[*]}]
set_input_transition -min 0.07  [get_ports {wbs_adr_i[*]}]
set_input_transition -min 0.07  [get_ports {wbs_dat_i[*]}]
set_input_transition -min 0.09  [get_ports {wbs_cyc_i}]
set_input_transition -min 0.09  [get_ports {wbs_sel_i[*]}]
set_input_transition -min 0.09  [get_ports {wbs_we_i}]
set_input_transition -min 0.15  [get_ports {wbs_stb_i}]

# Output delays
set_output_delay -max 0.7  -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
set_output_delay -max 1.0  -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
set_output_delay -max 3.62 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
set_output_delay -max 8.41 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
set_output_delay -min 0    -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
set_output_delay -min 0    -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
set_output_delay -min 1.13 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
set_output_delay -min 1.37 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
if { $::env(IO_SYNC) } {
    set out_ext_delay 4
    puts "\[INFO\]: Setting output ports external delay to: $out_ext_delay"
    set_output_delay -max [expr $out_ext_delay + 9.12] -clock [get_clocks {clk}] [get_ports {io_out[*]}]
    set_output_delay -max [expr $out_ext_delay + 9.32] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
    set_output_delay -min [expr $out_ext_delay + 2.34] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
    set_output_delay -min [expr $out_ext_delay + 3.9]  -clock [get_clocks {clk}] [get_ports {io_out[*]}]
}

# Output loads
set_load 0.19 [all_outputs]

Then, the PnR SDC file path was edited in the JSON file.

    "PNR_SDC_FILE": "dir::pnr.sdc",

Now the final ~/caravel_aes_accelerator/openlane/user_project_wrapper/config.json file will be:

Now let’s try re-running the flow:

[nix-shell:~/librelane]$ librelane ~/caravel_aes_accelerator/openlane/user_project_wrapper/config.json

The flow will finish successfully in ~1-2 hours and you will see:

Flow complete.

Re-checking the reports¶

There should still be no antenna violations, but this time, the STA report at xx-openroad-stapostpnr/summary.rpt should also show no issues:

┏━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━┳━━━━━━━━━━┳━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━┳━━━━━━━━━━━┳━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━━┳━━━━━━━━━━━━━━┓
┃              ┃ Hold Worst   ┃ Reg to Reg   ┃          ┃ Hold         ┃ of which Reg ┃ Setup Worst  ┃ Reg to Reg   ┃           ┃ Setup         ┃ of which Reg ┃ Max Cap       ┃ Max Slew     ┃
┃ Corner/Group ┃ Slack        ┃ Paths        ┃ Hold TNS ┃ Violations   ┃ to Reg       ┃ Slack        ┃ Paths        ┃ Setup TNS ┃ Violations    ┃ to Reg       ┃ Violations    ┃ Violations   ┃
┡━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━╇━━━━━━━━━━╇━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━╇━━━━━━━━━━━╇━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━━╇━━━━━━━━━━━━━━┩
│ Overall      │ 0.0486       │ 0.0486       │ 0.0000   │ 0            │ 0            │ 5.2837       │ 5.2837       │ 0.0000    │ 0             │ 0            │ 0             │ 0            │
│ nom_tt_025C… │ 0.2274       │ 0.2274       │ 0.0000   │ 0            │ 0            │ 11.0726      │ 15.1596      │ 0.0000    │ 0             │ 0            │ 0             │ 0            │
│ nom_ss_100C… │ 0.2414       │ 0.7146       │ 0.0000   │ 0            │ 0            │ 5.8981       │ 5.8981       │ 0.0000    │ 0             │ 0            │ 0             │ 0            │
│ nom_ff_n40C… │ 0.0497       │ 0.0497       │ 0.0000   │ 0            │ 0            │ 11.0978      │ 18.6822      │ 0.0000    │ 0             │ 0            │ 0             │ 0            │
│ min_tt_025C… │ 0.2253       │ 0.2253       │ 0.0000   │ 0            │ 0            │ 11.0640      │ 15.5219      │ 0.0000    │ 0             │ 0            │ 0             │ 0            │
│ min_ss_100C… │ 0.3307       │ 0.7108       │ 0.0000   │ 0            │ 0            │ 6.5295       │ 6.5295       │ 0.0000    │ 0             │ 0            │ 0             │ 0            │
│ min_ff_n40C… │ 0.0486       │ 0.0486       │ 0.0000   │ 0            │ 0            │ 11.0946      │ 18.9314      │ 0.0000    │ 0             │ 0            │ 0             │ 0            │
│ max_tt_025C… │ 0.2292       │ 0.2292       │ 0.0000   │ 0            │ 0            │ 11.0804      │ 14.7813      │ 0.0000    │ 0             │ 0            │ 0             │ 0            │
│ max_ss_100C… │ 0.1453       │ 0.7174       │ 0.0000   │ 0            │ 0            │ 5.2837       │ 5.2837       │ 0.0000    │ 0             │ 0            │ 0             │ 0            │
│ max_ff_n40C… │ 0.0509       │ 0.0509       │ 0.0000   │ 0            │ 0            │ 11.0951      │ 18.3978      │ 0.0000    │ 0             │ 0            │ 0             │ 0            │
└──────────────┴──────────────┴──────────────┴──────────┴──────────────┴──────────────┴──────────────┴──────────────┴───────────┴───────────────┴──────────────┴───────────────┴──────────────┘

Saving the views¶

To save the views, run the following script with the following arguments in order:

The directory of the project
The macro name
The successful run tag

[nix-shell:~/librelane]$ bash ~/caravel_aes_accelerator/openlane/copy_views.sh ~/caravel_aes_accelerator user_project_wrapper RUN_TAG

This will copy the physical views of the macro in the specified run to your project folder.

Congrats! Now you have another AES accelerator as a Caravel user project.

Option 2 — Full-Wrapper Flattening strategy¶

Configuration¶

Running the flow and dealing with the synthesis checks¶

Viewing the layout¶

Checking the reports¶

OpenROAD.CheckAntennas¶

OpenROAD.STAPostPnR¶

Magic.DRC¶

KLayout.DRC¶

Netgen.LVS¶

Re-running the flow with a modified configuration¶

Re-checking the reports¶

Saving the views¶

`OpenROAD.CheckAntennas`¶

`OpenROAD.STAPostPnR`¶

`Magic.DRC`¶

`KLayout.DRC`¶

`Netgen.LVS`¶