The LibreLane Documentation

LibreLane is a powerful and versatile infrastructure library that enables the construction of digital implementation flows for application specific integrated circuits (ASICs) based on open-source and commercial electronic design automation (EDA) tools.

LibreLane is:

  • Simple to use – Configure your entire ASIC implementation flow using one file.

  • Free and open source – With a complementary set of open-source process design kits (PDKs), design and implement your chip without signing a single document. Freely modify both the infrastructure, underlying tools, and PDK to fit your needs – you’re in control. Not a vendor.

  • Flexible and extensible – Create custom flows, both by simple modifications to the default flows in the configuration file, or by writing Python scripts or plugins to implement advanced functionality.

  • Hermetic – Rewind and explore alternative configurations without losing data; LibreLane captures explicit snapshots of the configuration and state of your design at every step.

  • Reproducible and traceable – LibreLane comes packaged with a verified environment of free EDA utilities with a simple goal in mind: same tools, same flow, same configuration; same result. Capture your modifications and engineering change orders (ECOs) as automated steps, and make your flow your documentation.

LibreLane includes two reference flows (Classic and Chip) that are built entirely using open-source EDA tools.

Follow the navigation element below (or check the sidebar on the left) to get started installing and using LibreLane.